SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T8,T23 |
1 | 0 | Covered | T8,T23,T1 |
1 | 1 | Covered | T8,T23,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 348369730 | 4299 | 0 | 0 |
g_div2.Div2Whole_A | 348369730 | 5185 | 0 | 0 |
g_div4.Div4Stepped_A | 173334766 | 4210 | 0 | 0 |
g_div4.Div4Whole_A | 173334766 | 4841 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 348369730 | 4299 | 0 | 0 |
T1 | 371423 | 44 | 0 | 0 |
T2 | 238385 | 0 | 0 | 0 |
T5 | 138986 | 0 | 0 | 0 |
T8 | 2283 | 8 | 0 | 0 |
T10 | 0 | 43 | 0 | 0 |
T17 | 18973 | 0 | 0 | 0 |
T18 | 1141 | 0 | 0 | 0 |
T19 | 1895 | 4 | 0 | 0 |
T20 | 14355 | 0 | 0 | 0 |
T21 | 2109 | 0 | 0 | 0 |
T22 | 0 | 11 | 0 | 0 |
T23 | 2429 | 1 | 0 | 0 |
T77 | 0 | 6 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
T99 | 0 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 348369730 | 5185 | 0 | 0 |
T1 | 371423 | 59 | 0 | 0 |
T2 | 238385 | 0 | 0 | 0 |
T5 | 138986 | 0 | 0 | 0 |
T8 | 2283 | 10 | 0 | 0 |
T10 | 0 | 43 | 0 | 0 |
T17 | 18973 | 0 | 0 | 0 |
T18 | 1141 | 0 | 0 | 0 |
T19 | 1895 | 6 | 0 | 0 |
T20 | 14355 | 0 | 0 | 0 |
T21 | 2109 | 0 | 0 | 0 |
T22 | 0 | 12 | 0 | 0 |
T23 | 2429 | 1 | 0 | 0 |
T77 | 0 | 8 | 0 | 0 |
T97 | 0 | 8 | 0 | 0 |
T98 | 0 | 4 | 0 | 0 |
T99 | 0 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 173334766 | 4210 | 0 | 0 |
T1 | 185381 | 42 | 0 | 0 |
T2 | 119153 | 0 | 0 | 0 |
T5 | 69372 | 0 | 0 | 0 |
T8 | 1272 | 8 | 0 | 0 |
T10 | 0 | 43 | 0 | 0 |
T17 | 9474 | 0 | 0 | 0 |
T18 | 517 | 0 | 0 | 0 |
T19 | 991 | 3 | 0 | 0 |
T20 | 7131 | 0 | 0 | 0 |
T21 | 988 | 0 | 0 | 0 |
T22 | 0 | 11 | 0 | 0 |
T23 | 1194 | 1 | 0 | 0 |
T77 | 0 | 6 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
T99 | 0 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 173334766 | 4841 | 0 | 0 |
T1 | 185381 | 45 | 0 | 0 |
T2 | 119153 | 0 | 0 | 0 |
T5 | 69372 | 0 | 0 | 0 |
T8 | 1272 | 10 | 0 | 0 |
T10 | 0 | 43 | 0 | 0 |
T17 | 9474 | 0 | 0 | 0 |
T18 | 517 | 0 | 0 | 0 |
T19 | 991 | 6 | 0 | 0 |
T20 | 7131 | 0 | 0 | 0 |
T21 | 988 | 0 | 0 | 0 |
T22 | 0 | 12 | 0 | 0 |
T23 | 1194 | 1 | 0 | 0 |
T77 | 0 | 5 | 0 | 0 |
T97 | 0 | 8 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
T99 | 0 | 6 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T8,T23 |
1 | 0 | Covered | T8,T23,T1 |
1 | 1 | Covered | T8,T23,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 348369730 | 4299 | 0 | 0 |
g_div2.Div2Whole_A | 348369730 | 5185 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 348369730 | 4299 | 0 | 0 |
T1 | 371423 | 44 | 0 | 0 |
T2 | 238385 | 0 | 0 | 0 |
T5 | 138986 | 0 | 0 | 0 |
T8 | 2283 | 8 | 0 | 0 |
T10 | 0 | 43 | 0 | 0 |
T17 | 18973 | 0 | 0 | 0 |
T18 | 1141 | 0 | 0 | 0 |
T19 | 1895 | 4 | 0 | 0 |
T20 | 14355 | 0 | 0 | 0 |
T21 | 2109 | 0 | 0 | 0 |
T22 | 0 | 11 | 0 | 0 |
T23 | 2429 | 1 | 0 | 0 |
T77 | 0 | 6 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
T99 | 0 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 348369730 | 5185 | 0 | 0 |
T1 | 371423 | 59 | 0 | 0 |
T2 | 238385 | 0 | 0 | 0 |
T5 | 138986 | 0 | 0 | 0 |
T8 | 2283 | 10 | 0 | 0 |
T10 | 0 | 43 | 0 | 0 |
T17 | 18973 | 0 | 0 | 0 |
T18 | 1141 | 0 | 0 | 0 |
T19 | 1895 | 6 | 0 | 0 |
T20 | 14355 | 0 | 0 | 0 |
T21 | 2109 | 0 | 0 | 0 |
T22 | 0 | 12 | 0 | 0 |
T23 | 2429 | 1 | 0 | 0 |
T77 | 0 | 8 | 0 | 0 |
T97 | 0 | 8 | 0 | 0 |
T98 | 0 | 4 | 0 | 0 |
T99 | 0 | 6 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T8,T23 |
1 | 0 | Covered | T8,T23,T1 |
1 | 1 | Covered | T8,T23,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 173334766 | 4210 | 0 | 0 |
g_div4.Div4Whole_A | 173334766 | 4841 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 173334766 | 4210 | 0 | 0 |
T1 | 185381 | 42 | 0 | 0 |
T2 | 119153 | 0 | 0 | 0 |
T5 | 69372 | 0 | 0 | 0 |
T8 | 1272 | 8 | 0 | 0 |
T10 | 0 | 43 | 0 | 0 |
T17 | 9474 | 0 | 0 | 0 |
T18 | 517 | 0 | 0 | 0 |
T19 | 991 | 3 | 0 | 0 |
T20 | 7131 | 0 | 0 | 0 |
T21 | 988 | 0 | 0 | 0 |
T22 | 0 | 11 | 0 | 0 |
T23 | 1194 | 1 | 0 | 0 |
T77 | 0 | 6 | 0 | 0 |
T97 | 0 | 7 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
T99 | 0 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 173334766 | 4841 | 0 | 0 |
T1 | 185381 | 45 | 0 | 0 |
T2 | 119153 | 0 | 0 | 0 |
T5 | 69372 | 0 | 0 | 0 |
T8 | 1272 | 10 | 0 | 0 |
T10 | 0 | 43 | 0 | 0 |
T17 | 9474 | 0 | 0 | 0 |
T18 | 517 | 0 | 0 | 0 |
T19 | 991 | 6 | 0 | 0 |
T20 | 7131 | 0 | 0 | 0 |
T21 | 988 | 0 | 0 | 0 |
T22 | 0 | 12 | 0 | 0 |
T23 | 1194 | 1 | 0 | 0 |
T77 | 0 | 5 | 0 | 0 |
T97 | 0 | 8 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
T99 | 0 | 6 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |