Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T8,T23
10CoveredT8,T23,T1
11CoveredT8,T23,T1

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 348369730 4299 0 0
g_div2.Div2Whole_A 348369730 5185 0 0
g_div4.Div4Stepped_A 173334766 4210 0 0
g_div4.Div4Whole_A 173334766 4841 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348369730 4299 0 0
T1 371423 44 0 0
T2 238385 0 0 0
T5 138986 0 0 0
T8 2283 8 0 0
T10 0 43 0 0
T17 18973 0 0 0
T18 1141 0 0 0
T19 1895 4 0 0
T20 14355 0 0 0
T21 2109 0 0 0
T22 0 11 0 0
T23 2429 1 0 0
T77 0 6 0 0
T97 0 7 0 0
T98 0 3 0 0
T99 0 6 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348369730 5185 0 0
T1 371423 59 0 0
T2 238385 0 0 0
T5 138986 0 0 0
T8 2283 10 0 0
T10 0 43 0 0
T17 18973 0 0 0
T18 1141 0 0 0
T19 1895 6 0 0
T20 14355 0 0 0
T21 2109 0 0 0
T22 0 12 0 0
T23 2429 1 0 0
T77 0 8 0 0
T97 0 8 0 0
T98 0 4 0 0
T99 0 6 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 173334766 4210 0 0
T1 185381 42 0 0
T2 119153 0 0 0
T5 69372 0 0 0
T8 1272 8 0 0
T10 0 43 0 0
T17 9474 0 0 0
T18 517 0 0 0
T19 991 3 0 0
T20 7131 0 0 0
T21 988 0 0 0
T22 0 11 0 0
T23 1194 1 0 0
T77 0 6 0 0
T97 0 7 0 0
T98 0 3 0 0
T99 0 6 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 173334766 4841 0 0
T1 185381 45 0 0
T2 119153 0 0 0
T5 69372 0 0 0
T8 1272 10 0 0
T10 0 43 0 0
T17 9474 0 0 0
T18 517 0 0 0
T19 991 6 0 0
T20 7131 0 0 0
T21 988 0 0 0
T22 0 12 0 0
T23 1194 1 0 0
T77 0 5 0 0
T97 0 8 0 0
T98 0 3 0 0
T99 0 6 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T8,T23
10CoveredT8,T23,T1
11CoveredT8,T23,T1

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 348369730 4299 0 0
g_div2.Div2Whole_A 348369730 5185 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348369730 4299 0 0
T1 371423 44 0 0
T2 238385 0 0 0
T5 138986 0 0 0
T8 2283 8 0 0
T10 0 43 0 0
T17 18973 0 0 0
T18 1141 0 0 0
T19 1895 4 0 0
T20 14355 0 0 0
T21 2109 0 0 0
T22 0 11 0 0
T23 2429 1 0 0
T77 0 6 0 0
T97 0 7 0 0
T98 0 3 0 0
T99 0 6 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348369730 5185 0 0
T1 371423 59 0 0
T2 238385 0 0 0
T5 138986 0 0 0
T8 2283 10 0 0
T10 0 43 0 0
T17 18973 0 0 0
T18 1141 0 0 0
T19 1895 6 0 0
T20 14355 0 0 0
T21 2109 0 0 0
T22 0 12 0 0
T23 2429 1 0 0
T77 0 8 0 0
T97 0 8 0 0
T98 0 4 0 0
T99 0 6 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T8,T23
10CoveredT8,T23,T1
11CoveredT8,T23,T1

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 173334766 4210 0 0
g_div4.Div4Whole_A 173334766 4841 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 173334766 4210 0 0
T1 185381 42 0 0
T2 119153 0 0 0
T5 69372 0 0 0
T8 1272 8 0 0
T10 0 43 0 0
T17 9474 0 0 0
T18 517 0 0 0
T19 991 3 0 0
T20 7131 0 0 0
T21 988 0 0 0
T22 0 11 0 0
T23 1194 1 0 0
T77 0 6 0 0
T97 0 7 0 0
T98 0 3 0 0
T99 0 6 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 173334766 4841 0 0
T1 185381 45 0 0
T2 119153 0 0 0
T5 69372 0 0 0
T8 1272 10 0 0
T10 0 43 0 0
T17 9474 0 0 0
T18 517 0 0 0
T19 991 6 0 0
T20 7131 0 0 0
T21 988 0 0 0
T22 0 12 0 0
T23 1194 1 0 0
T77 0 5 0 0
T97 0 8 0 0
T98 0 3 0 0
T99 0 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%