Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	491776113	475	0	0
StatusRise_A	491776113	475	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491776113	475	0	0
T4	410601	0	0	0
T17	3402	16	0	0
T18	3591	1	0	0
T19	5682	0	0	0
T20	21831	0	0	0
T21	3492	0	0	0
T22	7104	0	0	0
T26	153054	0	0	0
T32	2748	8	0	0
T33	0	15	0	0
T34	3150	0	0	0
T143	0	4	0	0
T144	0	7	0	0
T145	0	6	0	0
T146	0	9	0	0
T147	0	10	0	0
T148	0	9	0	0
T149	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491776113	475	0	0
T4	410601	0	0	0
T17	3402	16	0	0
T18	3591	1	0	0
T19	5682	0	0	0
T20	21831	0	0	0
T21	3492	0	0	0
T22	7104	0	0	0
T26	153054	0	0	0
T32	2748	8	0	0
T33	0	15	0	0
T34	3150	0	0	0
T143	0	4	0	0
T144	0	7	0	0
T145	0	6	0	0
T146	0	9	0	0
T147	0	10	0	0
T148	0	9	0	0
T149	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	163925371	154	0	0
StatusRise_A	163925371	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	154	0	0
T4	136867	0	0	0
T17	1134	6	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0
T26	51018	0	0	0
T32	916	2	0	0
T33	0	5	0	0
T34	1050	0	0	0
T143	0	2	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	154	0	0
T4	136867	0	0	0
T17	1134	6	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0
T26	51018	0	0	0
T32	916	2	0	0
T33	0	5	0	0
T34	1050	0	0	0
T143	0	2	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	163925371	159	0	0
StatusRise_A	163925371	159	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	159	0	0
T4	136867	0	0	0
T17	1134	3	0	0
T18	1197	1	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0
T26	51018	0	0	0
T32	916	3	0	0
T33	0	6	0	0
T34	1050	0	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0
T148	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	159	0	0
T4	136867	0	0	0
T17	1134	3	0	0
T18	1197	1	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0
T26	51018	0	0	0
T32	916	3	0	0
T33	0	6	0	0
T34	1050	0	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0
T148	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	163925371	162	0	0
StatusRise_A	163925371	162	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	162	0	0
T4	136867	0	0	0
T17	1134	7	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0
T26	51018	0	0	0
T32	916	3	0	0
T33	0	4	0	0
T34	1050	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	4	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163925371	162	0	0
T4	136867	0	0	0
T17	1134	7	0	0
T18	1197	0	0	0
T19	1894	0	0	0
T20	7277	0	0	0
T21	1164	0	0	0
T22	2368	0	0	0
T26	51018	0	0	0
T32	916	3	0	0
T33	0	4	0	0
T34	1050	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	4	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	0	2	0	0