Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	44934	0	0
CgEnOn_A	2147483647	35213	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44934	0	0
T1	3259502	244	0	0
T2	1529610	3	0	0
T4	579224	0	0	0
T5	1061588	48	0	0
T6	3431	3	0	0
T7	16551	9	0	0
T8	14844	3	0	0
T10	0	25	0	0
T17	216052	33	0	0
T18	12676	11	0	0
T19	21492	3	0	0
T20	206828	0	0	0
T21	10028	0	0	0
T22	45696	0	0	0
T23	15548	3	0	0
T26	425925	0	0	0
T32	14655	17	0	0
T33	0	35	0	0
T34	44175	1	0	0
T60	0	5	0	0
T101	0	1	0	0
T143	0	5	0	0
T144	0	10	0	0
T145	0	10	0	0
T146	0	15	0	0
T147	0	25	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35213	0	0
T1	3259502	263	0	0
T2	1529610	0	0	0
T4	837790	0	0	0
T5	1061588	47	0	0
T7	10800	11	0	0
T8	9512	0	0	0
T10	0	283	0	0
T17	216052	42	0	0
T18	12676	8	0	0
T19	21492	0	0	0
T20	244814	0	0	0
T21	14674	37	0	0
T22	67202	0	0	0
T23	10116	0	0	0
T26	425925	0	0	0
T32	14655	30	0	0
T33	0	63	0	0
T34	44175	5	0	0
T60	0	4	0	0
T101	0	2	0	0
T102	0	10	0	0
T103	0	3	0	0
T143	0	7	0	0
T144	0	14	0	0
T145	0	12	0	0
T146	0	17	0	0
T147	0	27	0	0
T148	0	6	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	173334352	168	0	0
CgEnOn_A	173334352	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173334352	168	0	0
T4	35507	0	0	0
T17	9474	3	0	0
T18	517	1	0	0
T19	991	0	0	0
T20	7130	0	0	0
T21	988	0	0	0
T22	5243	0	0	0
T26	29966	0	0	0
T32	1524	3	0	0
T33	0	6	0	0
T34	4540	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173334352	168	0	0
T4	35507	0	0	0
T17	9474	3	0	0
T18	517	1	0	0
T19	991	0	0	0
T20	7130	0	0	0
T21	988	0	0	0
T22	5243	0	0	0
T26	29966	0	0	0
T32	1524	3	0	0
T33	0	6	0	0
T34	4540	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	86666551	168	0	0
CgEnOn_A	86666551	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666551	168	0	0
T4	17755	0	0	0
T17	4737	3	0	0
T18	258	1	0	0
T19	496	0	0	0
T20	3565	0	0	0
T21	494	0	0	0
T22	2619	0	0	0
T26	14985	0	0	0
T32	762	3	0	0
T33	0	6	0	0
T34	2270	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666551	168	0	0
T4	17755	0	0	0
T17	4737	3	0	0
T18	258	1	0	0
T19	496	0	0	0
T20	3565	0	0	0
T21	494	0	0	0
T22	2619	0	0	0
T26	14985	0	0	0
T32	762	3	0	0
T33	0	6	0	0
T34	2270	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	86666551	168	0	0
CgEnOn_A	86666551	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666551	168	0	0
T4	17755	0	0	0
T17	4737	3	0	0
T18	258	1	0	0
T19	496	0	0	0
T20	3565	0	0	0
T21	494	0	0	0
T22	2619	0	0	0
T26	14985	0	0	0
T32	762	3	0	0
T33	0	6	0	0
T34	2270	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666551	168	0	0
T4	17755	0	0	0
T17	4737	3	0	0
T18	258	1	0	0
T19	496	0	0	0
T20	3565	0	0	0
T21	494	0	0	0
T22	2619	0	0	0
T26	14985	0	0	0
T32	762	3	0	0
T33	0	6	0	0
T34	2270	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	86666551	168	0	0
CgEnOn_A	86666551	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666551	168	0	0
T4	17755	0	0	0
T17	4737	3	0	0
T18	258	1	0	0
T19	496	0	0	0
T20	3565	0	0	0
T21	494	0	0	0
T22	2619	0	0	0
T26	14985	0	0	0
T32	762	3	0	0
T33	0	6	0	0
T34	2270	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666551	168	0	0
T4	17755	0	0	0
T17	4737	3	0	0
T18	258	1	0	0
T19	496	0	0	0
T20	3565	0	0	0
T21	494	0	0	0
T22	2619	0	0	0
T26	14985	0	0	0
T32	762	3	0	0
T33	0	6	0	0
T34	2270	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	348369267	168	0	0
CgEnOn_A	348369267	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348369267	168	0	0
T4	136867	0	0	0
T17	18972	3	0	0
T18	1140	1	0	0
T19	1894	0	0	0
T20	14354	0	0	0
T21	2109	0	0	0
T22	9096	0	0	0
T26	97952	0	0	0
T32	3168	3	0	0
T33	0	6	0	0
T34	9160	0	0	0
T60	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348369267	160	0	0
T4	136867	0	0	0
T17	18972	3	0	0
T18	1140	1	0	0
T19	1894	0	0	0
T20	14354	0	0	0
T21	2109	0	0	0
T22	9096	0	0	0
T26	97952	0	0	0
T32	3168	3	0	0
T33	0	6	0	0
T34	9160	0	0	0
T143	0	1	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T147	0	5	0	0
T148	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	372807150	158	0	0
CgEnOn_A	372807150	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	158	0	0
T4	142574	0	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T21	2197	0	0	0
T22	9476	0	0	0
T26	102037	0	0	0
T32	3027	2	0	0
T33	0	5	0	0
T34	9542	0	0	0
T143	0	2	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	155	0	0
T4	142574	0	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T21	2197	0	0	0
T22	9476	0	0	0
T26	102037	0	0	0
T32	3027	2	0	0
T33	0	5	0	0
T34	9542	0	0	0
T143	0	2	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	372807150	158	0	0
CgEnOn_A	372807150	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	158	0	0
T4	142574	0	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T21	2197	0	0	0
T22	9476	0	0	0
T26	102037	0	0	0
T32	3027	2	0	0
T33	0	5	0	0
T34	9542	0	0	0
T143	0	2	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	155	0	0
T4	142574	0	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T21	2197	0	0	0
T22	9476	0	0	0
T26	102037	0	0	0
T32	3027	2	0	0
T33	0	5	0	0
T34	9542	0	0	0
T143	0	2	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	4	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	178931655	164	0	0
CgEnOn_A	178931655	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178931655	164	0	0
T4	68437	0	0	0
T17	9554	7	0	0
T18	574	0	0	0
T19	947	0	0	0
T20	12937	0	0	0
T21	1055	0	0	0
T22	4548	0	0	0
T26	48978	0	0	0
T32	1623	3	0	0
T33	0	4	0	0
T34	4581	0	0	0
T63	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	4	0	0
T147	0	3	0	0
T148	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178931655	162	0	0
T4	68437	0	0	0
T17	9554	7	0	0
T18	574	0	0	0
T19	947	0	0	0
T20	12937	0	0	0
T21	1055	0	0	0
T22	4548	0	0	0
T26	48978	0	0	0
T32	1623	3	0	0
T33	0	4	0	0
T34	4581	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	4	0	0
T147	0	3	0	0
T148	0	3	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T32
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	86666551	7215	0	0
CgEnOn_A	86666551	4796	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666551	7215	0	0
T1	926898	70	0	0
T2	59576	1	0	0
T5	34686	14	0	0
T6	368	1	0	0
T7	621	1	0	0
T8	635	1	0	0
T17	4737	4	0	0
T18	258	2	0	0
T19	496	1	0	0
T23	596	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86666551	4796	0	0
T1	926898	60	0	0
T2	59576	0	0	0
T4	17755	0	0	0
T5	34686	11	0	0
T10	0	79	0	0
T17	4737	3	0	0
T18	258	1	0	0
T19	496	0	0	0
T20	3565	0	0	0
T21	494	11	0	0
T22	2619	0	0	0
T32	0	3	0	0
T33	0	6	0	0
T34	0	1	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T32
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	173334352	7242	0	0
CgEnOn_A	173334352	4823	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173334352	7242	0	0
T1	185381	69	0	0
T2	119152	1	0	0
T5	69372	14	0	0
T6	736	1	0	0
T7	1242	1	0	0
T8	1272	1	0	0
T17	9474	4	0	0
T18	517	2	0	0
T19	991	1	0	0
T23	1194	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173334352	4823	0	0
T1	185381	59	0	0
T2	119152	0	0	0
T4	35507	0	0	0
T5	69372	11	0	0
T10	0	73	0	0
T17	9474	3	0	0
T18	517	1	0	0
T19	991	0	0	0
T20	7130	0	0	0
T21	988	14	0	0
T22	5243	0	0	0
T32	0	3	0	0
T33	0	6	0	0
T34	0	1	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T32
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	348369267	7268	0	0
CgEnOn_A	348369267	4841	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348369267	7268	0	0
T1	371423	65	0	0
T2	238384	1	0	0
T5	138985	12	0	0
T6	1551	1	0	0
T7	2592	1	0	0
T8	2283	1	0	0
T17	18972	4	0	0
T18	1140	2	0	0
T19	1894	1	0	0
T23	2428	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348369267	4841	0	0
T1	371423	55	0	0
T2	238384	0	0	0
T4	136867	0	0	0
T5	138985	9	0	0
T10	0	73	0	0
T17	18972	3	0	0
T18	1140	1	0	0
T19	1894	0	0	0
T20	14354	0	0	0
T21	2109	12	0	0
T22	9096	0	0	0
T32	0	3	0	0
T33	0	6	0	0
T34	0	1	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T32,T33
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	178931655	7276	0	0
CgEnOn_A	178931655	4848	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178931655	7276	0	0
T1	189752	68	0	0
T2	119198	1	0	0
T5	95417	14	0	0
T6	776	1	0	0
T7	1296	1	0	0
T8	1142	1	0	0
T17	9554	8	0	0
T18	574	1	0	0
T19	947	1	0	0
T23	1214	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178931655	4848	0	0
T1	189752	58	0	0
T2	119198	0	0	0
T4	68437	0	0	0
T5	95417	11	0	0
T10	0	69	0	0
T11	0	25	0	0
T17	9554	7	0	0
T18	574	0	0	0
T19	947	0	0	0
T20	12937	0	0	0
T21	1055	10	0	0
T22	4548	0	0	0
T32	0	3	0	0
T33	0	4	0	0
T34	0	1	0	0
T103	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Covered	T7,T1,T5
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	372807150	3597	0	0
CgEnOn_A	372807150	3594	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	3597	0	0
T1	396512	40	0	0
T2	248325	0	0	0
T5	180782	8	0	0
T7	2700	6	0	0
T8	2378	0	0	0
T10	0	25	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T23	2529	0	0	0
T32	0	2	0	0
T33	0	5	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	3594	0	0
T1	396512	40	0	0
T2	248325	0	0	0
T5	180782	8	0	0
T7	2700	6	0	0
T8	2378	0	0	0
T10	0	25	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T23	2529	0	0	0
T32	0	2	0	0
T33	0	5	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Covered	T7,T1,T5
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	372807150	3630	0	0
CgEnOn_A	372807150	3627	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	3630	0	0
T1	396512	49	0	0
T2	248325	0	0	0
T5	180782	8	0	0
T7	2700	5	0	0
T8	2378	0	0	0
T10	0	33	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T23	2529	0	0	0
T32	0	2	0	0
T33	0	5	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	3627	0	0
T1	396512	49	0	0
T2	248325	0	0	0
T5	180782	8	0	0
T7	2700	5	0	0
T8	2378	0	0	0
T10	0	33	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T23	2529	0	0	0
T32	0	2	0	0
T33	0	5	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Covered	T7,T1,T5
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	372807150	3784	0	0
CgEnOn_A	372807150	3781	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	3784	0	0
T1	396512	42	0	0
T2	248325	0	0	0
T5	180782	6	0	0
T7	2700	3	0	0
T8	2378	0	0	0
T10	0	25	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T23	2529	0	0	0
T32	0	2	0	0
T33	0	5	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	3781	0	0
T1	396512	42	0	0
T2	248325	0	0	0
T5	180782	6	0	0
T7	2700	3	0	0
T8	2378	0	0	0
T10	0	25	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T23	2529	0	0	0
T32	0	2	0	0
T33	0	5	0	0
T34	0	1	0	0
T101	0	1	0	0
T102	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T17
1	0	Covered	T7,T1,T5
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	372807150	3602	0	0
CgEnOn_A	372807150	3599	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	3602	0	0
T1	396512	48	0	0
T2	248325	0	0	0
T5	180782	10	0	0
T7	2700	3	0	0
T8	2378	0	0	0
T10	0	28	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T23	2529	0	0	0
T32	0	2	0	0
T33	0	5	0	0
T34	0	1	0	0
T102	0	7	0	0
T103	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372807150	3599	0	0
T1	396512	48	0	0
T2	248325	0	0	0
T5	180782	10	0	0
T7	2700	3	0	0
T8	2378	0	0	0
T10	0	28	0	0
T17	20184	6	0	0
T18	1197	0	0	0
T19	1974	0	0	0
T20	26952	0	0	0
T23	2529	0	0	0
T32	0	2	0	0
T33	0	5	0	0
T34	0	1	0	0
T102	0	7	0	0
T103	0	1	0	0