Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	676050	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3880238

1

T7

24

T8

22

T9

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1112290	1			T7	44		T8	42		T9	3
values[0x0]	1581847	1			T7	15		T8	19		T9	5
values[0x1]	1862151	1			T7	18		T8	20		T9	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	372833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4183455

1

T7

28

T8

36

T9

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17714	1			T1	400		T5	1		T2	3
valid_sources[0x01]	17984	1			T1	740		T5	5		T3	2
valid_sources[0x02]	17703	1			T8	1		T1	408		T5	5
valid_sources[0x03]	17370	1			T1	409		T3	7		T38	1
valid_sources[0x04]	17287	1			T6	17		T1	249		T20	1
valid_sources[0x05]	17592	1			T24	1		T1	708		T5	2
valid_sources[0x06]	18241	1			T1	407		T19	1		T5	4
valid_sources[0x07]	17091	1			T6	1		T1	342		T5	5
valid_sources[0x08]	17257	1			T6	2		T1	549		T19	1
valid_sources[0x09]	18628	1			T1	243		T5	3		T2	3
valid_sources[0x0a]	18234	1			T8	1		T6	3		T1	844
valid_sources[0x0b]	16875	1			T8	1		T24	1		T1	221
valid_sources[0x0c]	18134	1			T8	1		T6	2		T1	193
valid_sources[0x0d]	17991	1			T7	3		T1	111		T5	2
valid_sources[0x0e]	17428	1			T6	3		T1	235		T5	2
valid_sources[0x0f]	17079	1			T1	387		T19	2		T2	5
valid_sources[0x10]	17920	1			T6	1		T1	399		T5	2
valid_sources[0x11]	17606	1			T24	1		T27	3		T6	4
valid_sources[0x12]	17788	1			T7	3		T6	10		T1	585
valid_sources[0x13]	19728	1			T1	423		T5	4		T3	1
valid_sources[0x14]	16748	1			T1	406		T5	1		T3	4
valid_sources[0x15]	17388	1			T24	1		T1	618		T5	1
valid_sources[0x16]	16822	1			T24	3		T6	1		T1	432
valid_sources[0x17]	17508	1			T6	15		T1	733		T19	3
valid_sources[0x18]	17145	1			T8	1		T27	1		T6	1
valid_sources[0x19]	17868	1			T6	8		T1	332		T19	1
valid_sources[0x1a]	18602	1			T24	1		T1	344		T5	5
valid_sources[0x1b]	17441	1			T8	1		T24	1		T6	1
valid_sources[0x1c]	16876	1			T6	2		T1	342		T5	1
valid_sources[0x1d]	17364	1			T1	131		T18	1		T3	7
valid_sources[0x1e]	19505	1			T24	1		T1	256		T2	3
valid_sources[0x1f]	18523	1			T6	11		T1	283		T5	2
valid_sources[0x20]	17246	1			T7	2		T6	5		T1	185
valid_sources[0x21]	16104	1			T24	1		T1	192		T5	8
valid_sources[0x22]	17034	1			T6	3		T1	198		T19	1
valid_sources[0x23]	18257	1			T24	2		T6	15		T1	387
valid_sources[0x24]	20968	1			T1	60		T5	8		T3	4
valid_sources[0x25]	16015	1			T1	273		T19	1		T5	5
valid_sources[0x26]	17411	1			T6	21		T1	277		T5	1
valid_sources[0x27]	18279	1			T1	388		T3	7		T13	6
valid_sources[0x28]	17418	1			T7	3		T1	333		T2	2
valid_sources[0x29]	17963	1			T6	3		T1	332		T5	12
valid_sources[0x2a]	18709	1			T27	6		T1	502		T5	5
valid_sources[0x2b]	17535	1			T27	3		T1	148		T5	1
valid_sources[0x2c]	19336	1			T8	2		T6	4		T1	678
valid_sources[0x2d]	17358	1			T24	1		T1	914		T21	1
valid_sources[0x2e]	18841	1			T9	3		T6	1		T1	506
valid_sources[0x2f]	17493	1			T24	1		T1	244		T18	1
valid_sources[0x30]	17144	1			T9	1		T6	3		T1	210
valid_sources[0x31]	16901	1			T6	2		T1	215		T5	5
valid_sources[0x32]	17348	1			T28	4		T6	4		T1	289
valid_sources[0x33]	18395	1			T24	1		T6	2		T1	290
valid_sources[0x34]	19079	1			T24	2		T1	324		T2	5
valid_sources[0x35]	18078	1			T6	2		T1	61		T5	1
valid_sources[0x36]	16341	1			T24	3		T1	163		T5	4
valid_sources[0x37]	17827	1			T24	1		T1	336		T19	2
valid_sources[0x38]	16766	1			T1	162		T19	2		T3	10
valid_sources[0x39]	17614	1			T1	611		T19	1		T5	9
valid_sources[0x3a]	17415	1			T7	4		T8	2		T1	392
valid_sources[0x3b]	18065	1			T6	7		T1	590		T3	9
valid_sources[0x3c]	17907	1			T1	1099		T5	3		T2	1
valid_sources[0x3d]	18600	1			T24	1		T6	10		T1	555
valid_sources[0x3e]	18320	1			T8	3		T1	138		T5	3
valid_sources[0x3f]	18188	1			T1	717		T5	4		T3	5
valid_sources[0x40]	17232	1			T6	10		T1	225		T5	4
valid_sources[0x41]	17313	1			T24	1		T6	3		T1	136
valid_sources[0x42]	17325	1			T6	7		T1	322		T19	1
valid_sources[0x43]	17577	1			T1	160		T5	5		T21	1
valid_sources[0x44]	17414	1			T8	1		T24	2		T6	2
valid_sources[0x45]	19415	1			T7	2		T1	312		T5	7
valid_sources[0x46]	16860	1			T6	4		T1	366		T21	1
valid_sources[0x47]	18612	1			T8	2		T6	9		T1	674
valid_sources[0x48]	18038	1			T6	14		T1	293		T5	1
valid_sources[0x49]	17974	1			T8	1		T1	355		T5	2
valid_sources[0x4a]	16447	1			T24	3		T1	87		T5	10
valid_sources[0x4b]	17401	1			T24	1		T6	1		T1	180
valid_sources[0x4c]	17138	1			T7	3		T1	234		T5	1
valid_sources[0x4d]	18140	1			T8	2		T1	272		T5	1
valid_sources[0x4e]	17454	1			T1	346		T19	1		T5	8
valid_sources[0x4f]	17109	1			T6	1		T1	531		T19	2
valid_sources[0x50]	18371	1			T24	1		T1	747		T5	4
valid_sources[0x51]	17158	1			T7	1		T24	1		T6	7
valid_sources[0x52]	19788	1			T24	1		T6	21		T1	581
valid_sources[0x53]	16980	1			T24	1		T1	290		T5	1
valid_sources[0x54]	16905	1			T24	2		T1	253		T5	2
valid_sources[0x55]	16867	1			T8	2		T24	2		T1	34
valid_sources[0x56]	17501	1			T7	2		T24	1		T1	428
valid_sources[0x57]	17787	1			T6	1		T1	423		T5	4
valid_sources[0x58]	17189	1			T6	4		T1	285		T5	6
valid_sources[0x59]	16849	1			T24	1		T1	286		T5	9
valid_sources[0x5a]	18033	1			T6	6		T1	351		T5	9
valid_sources[0x5b]	18485	1			T6	20		T1	444		T5	5
valid_sources[0x5c]	17871	1			T1	679		T19	1		T2	7
valid_sources[0x5d]	17262	1			T24	1		T6	12		T1	357
valid_sources[0x5e]	17212	1			T8	2		T24	1		T6	4
valid_sources[0x5f]	19279	1			T6	2		T1	889		T18	1
valid_sources[0x60]	17969	1			T6	3		T1	537		T5	1
valid_sources[0x61]	17412	1			T1	486		T5	2		T2	1
valid_sources[0x62]	17858	1			T8	1		T24	1		T1	197
valid_sources[0x63]	16256	1			T24	1		T1	566		T5	3
valid_sources[0x64]	19313	1			T7	5		T8	2		T1	283
valid_sources[0x65]	17414	1			T6	9		T1	763		T5	4
valid_sources[0x66]	17791	1			T7	3		T1	183		T5	1
valid_sources[0x67]	16371	1			T1	402		T2	1		T3	2
valid_sources[0x68]	17278	1			T8	1		T25	4		T6	5
valid_sources[0x69]	17511	1			T8	1		T6	10		T1	677
valid_sources[0x6a]	18661	1			T7	1		T1	278		T19	1
valid_sources[0x6b]	16810	1			T1	268		T18	1		T19	1
valid_sources[0x6c]	19080	1			T24	2		T6	1		T1	429
valid_sources[0x6d]	19231	1			T8	1		T6	6		T1	230
valid_sources[0x6e]	17421	1			T8	1		T6	10		T1	311
valid_sources[0x6f]	20601	1			T8	1		T24	2		T6	8
valid_sources[0x70]	19221	1			T27	1		T1	214		T2	1
valid_sources[0x71]	17455	1			T6	21		T1	232		T19	1
valid_sources[0x72]	17222	1			T7	2		T24	3		T6	1
valid_sources[0x73]	19076	1			T7	1		T24	2		T6	3
valid_sources[0x74]	17722	1			T7	8		T8	1		T6	19
valid_sources[0x75]	17287	1			T1	495		T5	2		T3	3
valid_sources[0x76]	16971	1			T6	5		T1	317		T18	1
valid_sources[0x77]	17539	1			T6	4		T1	240		T19	1
valid_sources[0x78]	17511	1			T6	11		T1	426		T5	2
valid_sources[0x79]	17849	1			T24	1		T1	225		T5	4
valid_sources[0x7a]	17069	1			T27	3		T6	3		T1	98
valid_sources[0x7b]	18458	1			T1	288		T19	1		T5	1
valid_sources[0x7c]	17147	1			T8	2		T24	1		T1	311
valid_sources[0x7d]	17715	1			T7	6		T24	2		T1	40
valid_sources[0x7e]	17999	1			T6	10		T1	400		T2	1
valid_sources[0x7f]	17673	1			T24	3		T6	5		T1	547
valid_sources[0x80]	18440	1			T24	1		T6	4		T1	480

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

975908

1

T7

19

T8

17

T9

1

values[0x0]

all_enables

biggest_size

1477342

1

T7

4

T8

5

T9

2

values[0x1]

all_enables

biggest_size

1426988

1

T7

1

T24

2

T25

1