Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T4
0	1	Covered	T6,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T6
1	0	Covered	T26,T29,T42
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1381455083	16407	0	0
GateOpen_A	1381455083	23109	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381455083	16407	0	0
T1	0	236	0	0
T3	0	17	0	0
T4	233487	0	0	0
T6	563718	29	0	0
T8	4648	4	0	0
T9	6472	0	0	0
T19	0	4	0	0
T20	0	6	0	0
T22	0	36	0	0
T24	9182	0	0	0
T25	8639	0	0	0
T26	17768	15	0	0
T27	5739	0	0	0
T28	4142	0	0	0
T29	3319	15	0	0
T134	0	26	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1381455083	23109	0	0
T1	0	264	0	0
T4	233487	56	0	0
T6	563718	49	0	0
T8	4648	4	0	0
T9	6472	4	0	0
T19	0	4	0	0
T20	0	6	0	0
T24	9182	0	0	0
T25	8639	0	0	0
T26	17768	19	0	0
T27	5739	0	0	0
T28	4142	4	0	0
T29	3319	19	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T4
0	1	Covered	T6,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T6
1	0	Covered	T26,T29,T42
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	152593278	3939	0	0
GateOpen_A	152593278	5613	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152593278	3939	0	0
T1	0	54	0	0
T3	0	4	0	0
T4	18485	0	0	0
T6	59217	6	0	0
T8	508	1	0	0
T9	715	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	0	8	0	0
T24	1005	0	0	0
T25	968	0	0	0
T26	2004	4	0	0
T27	655	0	0	0
T28	453	0	0	0
T29	366	4	0	0
T134	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152593278	5613	0	0
T1	0	61	0	0
T4	18485	14	0	0
T6	59217	11	0	0
T8	508	1	0	0
T9	715	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	1005	0	0	0
T25	968	0	0	0
T26	2004	5	0	0
T27	655	0	0	0
T28	453	1	0	0
T29	366	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T4
0	1	Covered	T6,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T6
1	0	Covered	T26,T29,T42
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	305187637	4169	0	0
GateOpen_A	305187637	5843	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187637	4169	0	0
T1	0	63	0	0
T3	0	5	0	0
T4	36966	0	0	0
T6	118437	8	0	0
T8	1016	1	0	0
T9	1430	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	0	10	0	0
T24	2010	0	0	0
T25	1935	0	0	0
T26	4008	4	0	0
T27	1313	0	0	0
T28	905	0	0	0
T29	732	4	0	0
T134	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187637	5843	0	0
T1	0	70	0	0
T4	36966	14	0	0
T6	118437	13	0	0
T8	1016	1	0	0
T9	1430	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	2010	0	0	0
T25	1935	0	0	0
T26	4008	5	0	0
T27	1313	0	0	0
T28	905	1	0	0
T29	732	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T4
0	1	Covered	T6,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T6
1	0	Covered	T26,T29,T42
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	611740454	4136	0	0
GateOpen_A	611740454	5813	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740454	4136	0	0
T1	0	61	0	0
T3	0	4	0	0
T4	118689	0	0	0
T6	236252	8	0	0
T8	2083	1	0	0
T9	2884	0	0	0
T19	0	1	0	0
T20	0	2	0	0
T22	0	10	0	0
T24	4111	0	0	0
T25	3824	0	0	0
T26	8123	4	0	0
T27	2514	0	0	0
T28	1856	0	0	0
T29	1487	4	0	0
T134	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740454	5813	0	0
T1	0	68	0	0
T4	118689	14	0	0
T6	236252	13	0	0
T8	2083	1	0	0
T9	2884	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T24	4111	0	0	0
T25	3824	0	0	0
T26	8123	5	0	0
T27	2514	0	0	0
T28	1856	1	0	0
T29	1487	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T4
0	1	Covered	T6,T1,T20
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T4,T6
1	0	Covered	T26,T29,T43
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	311933714	4163	0	0
GateOpen_A	311933714	5840	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311933714	4163	0	0
T1	0	58	0	0
T3	0	4	0	0
T4	59347	0	0	0
T6	149812	7	0	0
T8	1041	1	0	0
T9	1443	0	0	0
T19	0	1	0	0
T20	0	2	0	0
T22	0	8	0	0
T24	2056	0	0	0
T25	1912	0	0	0
T26	3633	3	0	0
T27	1257	0	0	0
T28	928	0	0	0
T29	734	3	0	0
T134	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311933714	5840	0	0
T1	0	65	0	0
T4	59347	14	0	0
T6	149812	12	0	0
T8	1041	1	0	0
T9	1443	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T24	2056	0	0	0
T25	1912	0	0	0
T26	3633	4	0	0
T27	1257	0	0	0
T28	928	1	0	0
T29	734	4	0	0