Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	874812225	82938	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874812225	82938	0	0
T1	1302715	1400	0	0
T2	599100	236	0	0
T3	698280	331	0	0
T5	237895	0	0	0
T11	0	100	0	0
T12	0	284	0	0
T13	0	498	0	0
T14	0	531	0	0
T15	0	3732	0	0
T16	0	391	0	0
T17	0	69	0	0
T18	6165	0	0	0
T19	12065	0	0	0
T20	4615	0	0	0
T21	12680	0	0	0
T22	7440	0	0	0
T23	4475	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174962445	12159	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	12159	0	0
T1	260543	217	0	0
T2	119820	33	0	0
T3	139656	53	0	0
T5	47579	0	0	0
T11	0	16	0	0
T12	0	37	0	0
T13	0	74	0	0
T14	0	75	0	0
T15	0	476	0	0
T16	0	51	0	0
T17	0	10	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174962445	12333	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	12333	0	0
T1	260543	210	0	0
T2	119820	32	0	0
T3	139656	53	0	0
T5	47579	0	0	0
T11	0	16	0	0
T12	0	34	0	0
T13	0	72	0	0
T14	0	74	0	0
T15	0	539	0	0
T16	0	52	0	0
T17	0	9	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174962445	16695	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	16695	0	0
T1	260543	279	0	0
T2	119820	49	0	0
T3	139656	67	0	0
T5	47579	0	0	0
T11	0	20	0	0
T12	0	56	0	0
T13	0	100	0	0
T14	0	119	0	0
T15	0	744	0	0
T16	0	81	0	0
T17	0	14	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174962445	16582	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	16582	0	0
T1	260543	280	0	0
T2	119820	46	0	0
T3	139656	67	0	0
T5	47579	0	0	0
T11	0	20	0	0
T12	0	57	0	0
T13	0	98	0	0
T14	0	103	0	0
T15	0	743	0	0
T16	0	79	0	0
T17	0	14	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	174962445	25169	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	25169	0	0
T1	260543	414	0	0
T2	119820	76	0	0
T3	139656	91	0	0
T5	47579	0	0	0
T11	0	28	0	0
T12	0	100	0	0
T13	0	154	0	0
T14	0	160	0	0
T15	0	1230	0	0
T16	0	128	0	0
T17	0	22	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0