Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T8 |
28 |
28 |
0 |
0 |
T9 |
28 |
28 |
0 |
0 |
T24 |
28 |
28 |
0 |
0 |
T25 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
T28 |
28 |
28 |
0 |
0 |
T29 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T4 |
1707217 |
657998 |
0 |
0 |
T7 |
60785 |
57120 |
0 |
0 |
T8 |
56615 |
52924 |
0 |
0 |
T9 |
56998 |
53151 |
0 |
0 |
T24 |
81812 |
79333 |
0 |
0 |
T25 |
60025 |
57804 |
0 |
0 |
T26 |
103515 |
100575 |
0 |
0 |
T27 |
60790 |
55105 |
0 |
0 |
T28 |
34747 |
33162 |
0 |
0 |
T29 |
40294 |
38066 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1049774670 |
1036881096 |
0 |
14490 |
T4 |
103848 |
31692 |
0 |
18 |
T7 |
13908 |
12972 |
0 |
18 |
T8 |
13014 |
12066 |
0 |
18 |
T9 |
8832 |
8154 |
0 |
18 |
T24 |
12846 |
12408 |
0 |
18 |
T25 |
5022 |
4788 |
0 |
18 |
T26 |
5898 |
5712 |
0 |
18 |
T27 |
12414 |
11124 |
0 |
18 |
T28 |
4866 |
4602 |
0 |
18 |
T29 |
9270 |
8700 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T4 |
647852 |
198588 |
0 |
21 |
T7 |
16247 |
15151 |
0 |
21 |
T8 |
15096 |
13997 |
0 |
21 |
T9 |
17844 |
16478 |
0 |
21 |
T24 |
25525 |
24666 |
0 |
21 |
T25 |
21429 |
20498 |
0 |
21 |
T26 |
38472 |
37135 |
0 |
21 |
T27 |
17128 |
15349 |
0 |
21 |
T28 |
11210 |
10621 |
0 |
21 |
T29 |
10737 |
10047 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
220970 |
0 |
0 |
T1 |
1118722 |
1285 |
0 |
0 |
T3 |
0 |
12 |
0 |
0 |
T4 |
647852 |
60 |
0 |
0 |
T6 |
386058 |
158 |
0 |
0 |
T7 |
9364 |
149 |
0 |
0 |
T8 |
8676 |
16 |
0 |
0 |
T9 |
17844 |
34 |
0 |
0 |
T18 |
0 |
61 |
0 |
0 |
T21 |
0 |
149 |
0 |
0 |
T23 |
0 |
19 |
0 |
0 |
T24 |
25525 |
220 |
0 |
0 |
T25 |
21429 |
12 |
0 |
0 |
T26 |
38472 |
24 |
0 |
0 |
T27 |
17128 |
154 |
0 |
0 |
T28 |
11210 |
15 |
0 |
0 |
T29 |
10737 |
29 |
0 |
0 |
T99 |
0 |
29 |
0 |
0 |
T135 |
0 |
23 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T4 |
955517 |
427133 |
0 |
0 |
T7 |
30630 |
28958 |
0 |
0 |
T8 |
28505 |
26822 |
0 |
0 |
T9 |
30322 |
28480 |
0 |
0 |
T24 |
43441 |
42220 |
0 |
0 |
T25 |
33574 |
32479 |
0 |
0 |
T26 |
59145 |
57689 |
0 |
0 |
T27 |
31248 |
28593 |
0 |
0 |
T28 |
18671 |
17900 |
0 |
0 |
T29 |
20287 |
19280 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T25,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T25,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T25,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T25,T27 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T25,T27 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T25,T27 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T25,T27 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T25,T27 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
611740057 |
607449179 |
0 |
0 |
T4 |
118688 |
36433 |
0 |
0 |
T7 |
2247 |
2098 |
0 |
0 |
T8 |
2082 |
1934 |
0 |
0 |
T9 |
2884 |
2667 |
0 |
0 |
T24 |
4111 |
3977 |
0 |
0 |
T25 |
3823 |
3661 |
0 |
0 |
T26 |
8122 |
7878 |
0 |
0 |
T27 |
2514 |
2256 |
0 |
0 |
T28 |
1856 |
1762 |
0 |
0 |
T29 |
1487 |
1394 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
611740057 |
607442141 |
0 |
2415 |
T4 |
118688 |
36388 |
0 |
3 |
T7 |
2247 |
2095 |
0 |
3 |
T8 |
2082 |
1931 |
0 |
3 |
T9 |
2884 |
2664 |
0 |
3 |
T24 |
4111 |
3974 |
0 |
3 |
T25 |
3823 |
3658 |
0 |
3 |
T26 |
8122 |
7875 |
0 |
3 |
T27 |
2514 |
2253 |
0 |
3 |
T28 |
1856 |
1759 |
0 |
3 |
T29 |
1487 |
1391 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
611740057 |
31335 |
0 |
0 |
T1 |
597636 |
552 |
0 |
0 |
T3 |
0 |
8 |
0 |
0 |
T4 |
118688 |
0 |
0 |
0 |
T6 |
236252 |
64 |
0 |
0 |
T9 |
2884 |
11 |
0 |
0 |
T18 |
0 |
28 |
0 |
0 |
T21 |
0 |
75 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
T24 |
4111 |
0 |
0 |
0 |
T25 |
3823 |
5 |
0 |
0 |
T26 |
8122 |
0 |
0 |
0 |
T27 |
2514 |
41 |
0 |
0 |
T28 |
1856 |
3 |
0 |
0 |
T29 |
1487 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T25,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T25,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T25,T27 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T25,T27 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T25,T27 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T25,T27 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T25,T27 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T25,T27 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172813516 |
0 |
2415 |
T4 |
17308 |
5282 |
0 |
3 |
T7 |
2318 |
2162 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
1472 |
1359 |
0 |
3 |
T24 |
2141 |
2068 |
0 |
3 |
T25 |
837 |
798 |
0 |
3 |
T26 |
983 |
952 |
0 |
3 |
T27 |
2069 |
1854 |
0 |
3 |
T28 |
811 |
767 |
0 |
3 |
T29 |
1545 |
1450 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
19309 |
0 |
0 |
T1 |
260543 |
338 |
0 |
0 |
T3 |
0 |
4 |
0 |
0 |
T4 |
17308 |
0 |
0 |
0 |
T6 |
74903 |
53 |
0 |
0 |
T9 |
1472 |
7 |
0 |
0 |
T18 |
0 |
17 |
0 |
0 |
T21 |
0 |
26 |
0 |
0 |
T23 |
0 |
7 |
0 |
0 |
T24 |
2141 |
0 |
0 |
0 |
T25 |
837 |
3 |
0 |
0 |
T26 |
983 |
0 |
0 |
0 |
T27 |
2069 |
43 |
0 |
0 |
T28 |
811 |
4 |
0 |
0 |
T29 |
1545 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172813516 |
0 |
2415 |
T4 |
17308 |
5282 |
0 |
3 |
T7 |
2318 |
2162 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
1472 |
1359 |
0 |
3 |
T24 |
2141 |
2068 |
0 |
3 |
T25 |
837 |
798 |
0 |
3 |
T26 |
983 |
952 |
0 |
3 |
T27 |
2069 |
1854 |
0 |
3 |
T28 |
811 |
767 |
0 |
3 |
T29 |
1545 |
1450 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
22434 |
0 |
0 |
T1 |
260543 |
395 |
0 |
0 |
T4 |
17308 |
0 |
0 |
0 |
T6 |
74903 |
41 |
0 |
0 |
T9 |
1472 |
4 |
0 |
0 |
T18 |
0 |
16 |
0 |
0 |
T21 |
0 |
48 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T24 |
2141 |
0 |
0 |
0 |
T25 |
837 |
0 |
0 |
0 |
T26 |
983 |
0 |
0 |
0 |
T27 |
2069 |
26 |
0 |
0 |
T28 |
811 |
2 |
0 |
0 |
T29 |
1545 |
0 |
0 |
0 |
T99 |
0 |
29 |
0 |
0 |
T135 |
0 |
23 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
647090467 |
0 |
0 |
T4 |
123637 |
77011 |
0 |
0 |
T7 |
2341 |
2286 |
0 |
0 |
T8 |
2169 |
2114 |
0 |
0 |
T9 |
3004 |
2892 |
0 |
0 |
T24 |
4283 |
4185 |
0 |
0 |
T25 |
3983 |
3900 |
0 |
0 |
T26 |
7096 |
6985 |
0 |
0 |
T27 |
2619 |
2493 |
0 |
0 |
T28 |
1933 |
1878 |
0 |
0 |
T29 |
1540 |
1514 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
647090467 |
0 |
0 |
T4 |
123637 |
77011 |
0 |
0 |
T7 |
2341 |
2286 |
0 |
0 |
T8 |
2169 |
2114 |
0 |
0 |
T9 |
3004 |
2892 |
0 |
0 |
T24 |
4283 |
4185 |
0 |
0 |
T25 |
3983 |
3900 |
0 |
0 |
T26 |
7096 |
6985 |
0 |
0 |
T27 |
2619 |
2493 |
0 |
0 |
T28 |
1933 |
1878 |
0 |
0 |
T29 |
1540 |
1514 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
611740057 |
609633143 |
0 |
0 |
T4 |
118688 |
73928 |
0 |
0 |
T7 |
2247 |
2194 |
0 |
0 |
T8 |
2082 |
2030 |
0 |
0 |
T9 |
2884 |
2776 |
0 |
0 |
T24 |
4111 |
4018 |
0 |
0 |
T25 |
3823 |
3743 |
0 |
0 |
T26 |
8122 |
8015 |
0 |
0 |
T27 |
2514 |
2393 |
0 |
0 |
T28 |
1856 |
1803 |
0 |
0 |
T29 |
1487 |
1462 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
611740057 |
609633143 |
0 |
0 |
T4 |
118688 |
73928 |
0 |
0 |
T7 |
2247 |
2194 |
0 |
0 |
T8 |
2082 |
2030 |
0 |
0 |
T9 |
2884 |
2776 |
0 |
0 |
T24 |
4111 |
4018 |
0 |
0 |
T25 |
3823 |
3743 |
0 |
0 |
T26 |
8122 |
8015 |
0 |
0 |
T27 |
2514 |
2393 |
0 |
0 |
T28 |
1856 |
1803 |
0 |
0 |
T29 |
1487 |
1462 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305187244 |
305187244 |
0 |
0 |
T4 |
36966 |
36966 |
0 |
0 |
T7 |
1097 |
1097 |
0 |
0 |
T8 |
1015 |
1015 |
0 |
0 |
T9 |
1429 |
1429 |
0 |
0 |
T24 |
2009 |
2009 |
0 |
0 |
T25 |
1935 |
1935 |
0 |
0 |
T26 |
4008 |
4008 |
0 |
0 |
T27 |
1313 |
1313 |
0 |
0 |
T28 |
905 |
905 |
0 |
0 |
T29 |
731 |
731 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305187244 |
305187244 |
0 |
0 |
T4 |
36966 |
36966 |
0 |
0 |
T7 |
1097 |
1097 |
0 |
0 |
T8 |
1015 |
1015 |
0 |
0 |
T9 |
1429 |
1429 |
0 |
0 |
T24 |
2009 |
2009 |
0 |
0 |
T25 |
1935 |
1935 |
0 |
0 |
T26 |
4008 |
4008 |
0 |
0 |
T27 |
1313 |
1313 |
0 |
0 |
T28 |
905 |
905 |
0 |
0 |
T29 |
731 |
731 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152592897 |
152592897 |
0 |
0 |
T4 |
18484 |
18484 |
0 |
0 |
T7 |
549 |
549 |
0 |
0 |
T8 |
508 |
508 |
0 |
0 |
T9 |
715 |
715 |
0 |
0 |
T24 |
1005 |
1005 |
0 |
0 |
T25 |
967 |
967 |
0 |
0 |
T26 |
2004 |
2004 |
0 |
0 |
T27 |
655 |
655 |
0 |
0 |
T28 |
452 |
452 |
0 |
0 |
T29 |
366 |
366 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152592897 |
152592897 |
0 |
0 |
T4 |
18484 |
18484 |
0 |
0 |
T7 |
549 |
549 |
0 |
0 |
T8 |
508 |
508 |
0 |
0 |
T9 |
715 |
715 |
0 |
0 |
T24 |
1005 |
1005 |
0 |
0 |
T25 |
967 |
967 |
0 |
0 |
T26 |
2004 |
2004 |
0 |
0 |
T27 |
655 |
655 |
0 |
0 |
T28 |
452 |
452 |
0 |
0 |
T29 |
366 |
366 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
311933295 |
310862446 |
0 |
0 |
T4 |
59346 |
36966 |
0 |
0 |
T7 |
1124 |
1098 |
0 |
0 |
T8 |
1041 |
1015 |
0 |
0 |
T9 |
1442 |
1388 |
0 |
0 |
T24 |
2055 |
2009 |
0 |
0 |
T25 |
1912 |
1872 |
0 |
0 |
T26 |
3633 |
3579 |
0 |
0 |
T27 |
1257 |
1197 |
0 |
0 |
T28 |
927 |
902 |
0 |
0 |
T29 |
733 |
721 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
311933295 |
310862446 |
0 |
0 |
T4 |
59346 |
36966 |
0 |
0 |
T7 |
1124 |
1098 |
0 |
0 |
T8 |
1041 |
1015 |
0 |
0 |
T9 |
1442 |
1388 |
0 |
0 |
T24 |
2055 |
2009 |
0 |
0 |
T25 |
1912 |
1872 |
0 |
0 |
T26 |
3633 |
3579 |
0 |
0 |
T27 |
1257 |
1197 |
0 |
0 |
T28 |
927 |
902 |
0 |
0 |
T29 |
733 |
721 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172813516 |
0 |
2415 |
T4 |
17308 |
5282 |
0 |
3 |
T7 |
2318 |
2162 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
1472 |
1359 |
0 |
3 |
T24 |
2141 |
2068 |
0 |
3 |
T25 |
837 |
798 |
0 |
3 |
T26 |
983 |
952 |
0 |
3 |
T27 |
2069 |
1854 |
0 |
3 |
T28 |
811 |
767 |
0 |
3 |
T29 |
1545 |
1450 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172813516 |
0 |
2415 |
T4 |
17308 |
5282 |
0 |
3 |
T7 |
2318 |
2162 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
1472 |
1359 |
0 |
3 |
T24 |
2141 |
2068 |
0 |
3 |
T25 |
837 |
798 |
0 |
3 |
T26 |
983 |
952 |
0 |
3 |
T27 |
2069 |
1854 |
0 |
3 |
T28 |
811 |
767 |
0 |
3 |
T29 |
1545 |
1450 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172813516 |
0 |
2415 |
T4 |
17308 |
5282 |
0 |
3 |
T7 |
2318 |
2162 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
1472 |
1359 |
0 |
3 |
T24 |
2141 |
2068 |
0 |
3 |
T25 |
837 |
798 |
0 |
3 |
T26 |
983 |
952 |
0 |
3 |
T27 |
2069 |
1854 |
0 |
3 |
T28 |
811 |
767 |
0 |
3 |
T29 |
1545 |
1450 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172813516 |
0 |
2415 |
T4 |
17308 |
5282 |
0 |
3 |
T7 |
2318 |
2162 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
1472 |
1359 |
0 |
3 |
T24 |
2141 |
2068 |
0 |
3 |
T25 |
837 |
798 |
0 |
3 |
T26 |
983 |
952 |
0 |
3 |
T27 |
2069 |
1854 |
0 |
3 |
T28 |
811 |
767 |
0 |
3 |
T29 |
1545 |
1450 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172813516 |
0 |
2415 |
T4 |
17308 |
5282 |
0 |
3 |
T7 |
2318 |
2162 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
1472 |
1359 |
0 |
3 |
T24 |
2141 |
2068 |
0 |
3 |
T25 |
837 |
798 |
0 |
3 |
T26 |
983 |
952 |
0 |
3 |
T27 |
2069 |
1854 |
0 |
3 |
T28 |
811 |
767 |
0 |
3 |
T29 |
1545 |
1450 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172813516 |
0 |
2415 |
T4 |
17308 |
5282 |
0 |
3 |
T7 |
2318 |
2162 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
1472 |
1359 |
0 |
3 |
T24 |
2141 |
2068 |
0 |
3 |
T25 |
837 |
798 |
0 |
3 |
T26 |
983 |
952 |
0 |
3 |
T27 |
2069 |
1854 |
0 |
3 |
T28 |
811 |
767 |
0 |
3 |
T29 |
1545 |
1450 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
172820712 |
0 |
0 |
T4 |
17308 |
5327 |
0 |
0 |
T7 |
2318 |
2165 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
1472 |
1362 |
0 |
0 |
T24 |
2141 |
2071 |
0 |
0 |
T25 |
837 |
801 |
0 |
0 |
T26 |
983 |
955 |
0 |
0 |
T27 |
2069 |
1857 |
0 |
0 |
T28 |
811 |
770 |
0 |
0 |
T29 |
1545 |
1453 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644779436 |
0 |
2415 |
T4 |
123637 |
37909 |
0 |
3 |
T7 |
2341 |
2183 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
3004 |
2774 |
0 |
3 |
T24 |
4283 |
4139 |
0 |
3 |
T25 |
3983 |
3811 |
0 |
3 |
T26 |
7096 |
6839 |
0 |
3 |
T27 |
2619 |
2347 |
0 |
3 |
T28 |
1933 |
1832 |
0 |
3 |
T29 |
1540 |
1439 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
36726 |
0 |
0 |
T4 |
123637 |
15 |
0 |
0 |
T7 |
2341 |
40 |
0 |
0 |
T8 |
2169 |
4 |
0 |
0 |
T9 |
3004 |
5 |
0 |
0 |
T24 |
4283 |
51 |
0 |
0 |
T25 |
3983 |
1 |
0 |
0 |
T26 |
7096 |
5 |
0 |
0 |
T27 |
2619 |
16 |
0 |
0 |
T28 |
1933 |
1 |
0 |
0 |
T29 |
1540 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644779436 |
0 |
2415 |
T4 |
123637 |
37909 |
0 |
3 |
T7 |
2341 |
2183 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
3004 |
2774 |
0 |
3 |
T24 |
4283 |
4139 |
0 |
3 |
T25 |
3983 |
3811 |
0 |
3 |
T26 |
7096 |
6839 |
0 |
3 |
T27 |
2619 |
2347 |
0 |
3 |
T28 |
1933 |
1832 |
0 |
3 |
T29 |
1540 |
1439 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
37116 |
0 |
0 |
T4 |
123637 |
15 |
0 |
0 |
T7 |
2341 |
35 |
0 |
0 |
T8 |
2169 |
4 |
0 |
0 |
T9 |
3004 |
1 |
0 |
0 |
T24 |
4283 |
55 |
0 |
0 |
T25 |
3983 |
1 |
0 |
0 |
T26 |
7096 |
5 |
0 |
0 |
T27 |
2619 |
10 |
0 |
0 |
T28 |
1933 |
1 |
0 |
0 |
T29 |
1540 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644779436 |
0 |
2415 |
T4 |
123637 |
37909 |
0 |
3 |
T7 |
2341 |
2183 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
3004 |
2774 |
0 |
3 |
T24 |
4283 |
4139 |
0 |
3 |
T25 |
3983 |
3811 |
0 |
3 |
T26 |
7096 |
6839 |
0 |
3 |
T27 |
2619 |
2347 |
0 |
3 |
T28 |
1933 |
1832 |
0 |
3 |
T29 |
1540 |
1439 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
36937 |
0 |
0 |
T4 |
123637 |
15 |
0 |
0 |
T7 |
2341 |
41 |
0 |
0 |
T8 |
2169 |
4 |
0 |
0 |
T9 |
3004 |
5 |
0 |
0 |
T24 |
4283 |
57 |
0 |
0 |
T25 |
3983 |
1 |
0 |
0 |
T26 |
7096 |
9 |
0 |
0 |
T27 |
2619 |
10 |
0 |
0 |
T28 |
1933 |
3 |
0 |
0 |
T29 |
1540 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644779436 |
0 |
2415 |
T4 |
123637 |
37909 |
0 |
3 |
T7 |
2341 |
2183 |
0 |
3 |
T8 |
2169 |
2011 |
0 |
3 |
T9 |
3004 |
2774 |
0 |
3 |
T24 |
4283 |
4139 |
0 |
3 |
T25 |
3983 |
3811 |
0 |
3 |
T26 |
7096 |
6839 |
0 |
3 |
T27 |
2619 |
2347 |
0 |
3 |
T28 |
1933 |
1832 |
0 |
3 |
T29 |
1540 |
1439 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
37113 |
0 |
0 |
T4 |
123637 |
15 |
0 |
0 |
T7 |
2341 |
33 |
0 |
0 |
T8 |
2169 |
4 |
0 |
0 |
T9 |
3004 |
1 |
0 |
0 |
T24 |
4283 |
57 |
0 |
0 |
T25 |
3983 |
1 |
0 |
0 |
T26 |
7096 |
5 |
0 |
0 |
T27 |
2619 |
8 |
0 |
0 |
T28 |
1933 |
1 |
0 |
0 |
T29 |
1540 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T24 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
644786484 |
0 |
0 |
T4 |
123637 |
37954 |
0 |
0 |
T7 |
2341 |
2186 |
0 |
0 |
T8 |
2169 |
2014 |
0 |
0 |
T9 |
3004 |
2777 |
0 |
0 |
T24 |
4283 |
4142 |
0 |
0 |
T25 |
3983 |
3814 |
0 |
0 |
T26 |
7096 |
6842 |
0 |
0 |
T27 |
2619 |
2350 |
0 |
0 |
T28 |
1933 |
1835 |
0 |
0 |
T29 |
1540 |
1442 |
0 |
0 |