Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	174962445	172664151	0	0
AllClkBypReqTrue_A	174962445	154215	0	0
IoClkBypReqFalse_A	174962445	172573606	0	2415
IoClkBypReqTrue_A	174962445	240068	0	0
LcClkBypAckFalse_A	174962445	172676802	0	0
LcClkBypAckTrue_A	174962445	141564	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	172664151	0	0
T4	17308	5312	0	0
T7	2318	2164	0	0
T8	2169	2013	0	0
T9	1472	1361	0	0
T24	2141	2070	0	0
T25	837	800	0	0
T26	983	954	0	0
T27	2069	1752	0	0
T28	811	769	0	0
T29	1545	1452	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	154215	0	0
T1	260543	2531	0	0
T2	119820	0	0	0
T5	47579	0	0	0
T6	74903	287	0	0
T18	1233	30	0	0
T19	2413	0	0	0
T20	923	0	0	0
T21	0	380	0	0
T23	0	31	0	0
T27	2069	104	0	0
T28	811	0	0	0
T29	1545	0	0	0
T86	0	252	0	0
T99	0	212	0	0
T107	0	69	0	0
T108	0	200	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	172573606	0	2415
T4	17308	5282	0	3
T7	2318	2162	0	3
T8	2169	2011	0	3
T9	1472	1226	0	3
T24	2141	2068	0	3
T25	837	757	0	3
T26	983	952	0	3
T27	2069	1582	0	3
T28	811	731	0	3
T29	1545	1450	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	240068	0	0
T1	260543	3600	0	0
T3	0	70	0	0
T4	17308	0	0	0
T6	74903	683	0	0
T9	1472	133	0	0
T18	0	178	0	0
T21	0	332	0	0
T23	0	51	0	0
T24	2141	0	0	0
T25	837	41	0	0
T26	983	0	0	0
T27	2069	272	0	0
T28	811	36	0	0
T29	1545	0	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	172676802	0	0
T4	17308	5312	0	0
T7	2318	2164	0	0
T8	2169	2013	0	0
T9	1472	1321	0	0
T24	2141	2070	0	0
T25	837	772	0	0
T26	983	954	0	0
T27	2069	1730	0	0
T28	811	768	0	0
T29	1545	1452	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	141564	0	0
T1	260543	2512	0	0
T3	0	25	0	0
T4	17308	0	0	0
T6	74903	305	0	0
T9	1472	40	0	0
T18	0	88	0	0
T21	0	180	0	0
T24	2141	0	0	0
T25	837	28	0	0
T26	983	0	0	0
T27	2069	126	0	0
T28	811	1	0	0
T29	1545	0	0	0
T99	0	163	0	0