Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	17624	0	0
TransStop_A	2147483647	8835	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17624	0	0
T1	0	289	0	0
T3	0	35	0	0
T4	494552	0	0	0
T6	0	69	0	0
T7	9368	19	0	0
T8	8680	4	0	0
T9	12020	0	0	0
T12	0	12	0	0
T19	0	4	0	0
T24	17136	37	0	0
T25	15932	0	0	0
T26	28384	0	0	0
T27	10480	0	0	0
T28	7736	0	0	0
T29	6164	0	0	0
T109	0	9	0	0
T110	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8835	0	0
T1	0	141	0	0
T3	0	17	0	0
T4	494552	0	0	0
T6	0	33	0	0
T7	9368	8	0	0
T8	8680	4	0	0
T9	12020	0	0	0
T12	0	11	0	0
T13	0	6	0	0
T19	0	4	0	0
T24	17136	16	0	0
T25	15932	0	0	0
T26	28384	0	0	0
T27	10480	0	0	0
T28	7736	0	0	0
T29	6164	0	0	0
T109	0	3	0	0
T110	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	649318472	4436	0	0
TransStop_A	649318472	2250	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318472	4436	0	0
T1	0	74	0	0
T3	0	8	0	0
T4	123638	0	0	0
T6	0	15	0	0
T7	2342	4	0	0
T8	2170	1	0	0
T9	3005	0	0	0
T12	0	3	0	0
T19	0	1	0	0
T24	4284	7	0	0
T25	3983	0	0	0
T26	7096	0	0	0
T27	2620	0	0	0
T28	1934	0	0	0
T29	1541	0	0	0
T109	0	1	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318472	2250	0	0
T1	0	40	0	0
T3	0	2	0	0
T4	123638	0	0	0
T6	0	8	0	0
T7	2342	2	0	0
T8	2170	1	0	0
T9	3005	0	0	0
T12	0	3	0	0
T13	0	3	0	0
T19	0	1	0	0
T24	4284	2	0	0
T25	3983	0	0	0
T26	7096	0	0	0
T27	2620	0	0	0
T28	1934	0	0	0
T29	1541	0	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	649318472	4406	0	0
TransStop_A	649318472	2189	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318472	4406	0	0
T1	0	68	0	0
T3	0	10	0	0
T4	123638	0	0	0
T6	0	14	0	0
T7	2342	5	0	0
T8	2170	1	0	0
T9	3005	0	0	0
T12	0	4	0	0
T19	0	1	0	0
T24	4284	10	0	0
T25	3983	0	0	0
T26	7096	0	0	0
T27	2620	0	0	0
T28	1934	0	0	0
T29	1541	0	0	0
T109	0	2	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318472	2189	0	0
T1	0	31	0	0
T3	0	5	0	0
T4	123638	0	0	0
T6	0	8	0	0
T7	2342	2	0	0
T8	2170	1	0	0
T9	3005	0	0	0
T12	0	4	0	0
T19	0	1	0	0
T24	4284	5	0	0
T25	3983	0	0	0
T26	7096	0	0	0
T27	2620	0	0	0
T28	1934	0	0	0
T29	1541	0	0	0
T109	0	1	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	649318472	4398	0	0
TransStop_A	649318472	2203	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318472	4398	0	0
T1	0	69	0	0
T3	0	10	0	0
T4	123638	0	0	0
T6	0	21	0	0
T7	2342	7	0	0
T8	2170	1	0	0
T9	3005	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T24	4284	7	0	0
T25	3983	0	0	0
T26	7096	0	0	0
T27	2620	0	0	0
T28	1934	0	0	0
T29	1541	0	0	0
T109	0	4	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318472	2203	0	0
T1	0	32	0	0
T3	0	6	0	0
T4	123638	0	0	0
T6	0	8	0	0
T7	2342	2	0	0
T8	2170	1	0	0
T9	3005	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T24	4284	4	0	0
T25	3983	0	0	0
T26	7096	0	0	0
T27	2620	0	0	0
T28	1934	0	0	0
T29	1541	0	0	0
T109	0	2	0	0
T110	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	649318472	4384	0	0
TransStop_A	649318472	2193	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318472	4384	0	0
T1	0	78	0	0
T3	0	7	0	0
T4	123638	0	0	0
T6	0	19	0	0
T7	2342	3	0	0
T8	2170	1	0	0
T9	3005	0	0	0
T12	0	4	0	0
T19	0	1	0	0
T24	4284	13	0	0
T25	3983	0	0	0
T26	7096	0	0	0
T27	2620	0	0	0
T28	1934	0	0	0
T29	1541	0	0	0
T109	0	2	0	0
T110	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318472	2193	0	0
T1	0	38	0	0
T3	0	4	0	0
T4	123638	0	0	0
T6	0	9	0	0
T7	2342	2	0	0
T8	2170	1	0	0
T9	3005	0	0	0
T12	0	3	0	0
T13	0	3	0	0
T19	0	1	0	0
T24	4284	5	0	0
T25	3983	0	0	0
T26	7096	0	0	0
T27	2620	0	0	0
T28	1934	0	0	0
T29	1541	0	0	0
T110	0	1	0	0