Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10CoveredT9,T25,T27 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT9,T25,T27
11CoveredT9,T25,T27 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T25,T27
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 762597289 762594874 0 0
selKnown1 1835220171 1835217756 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 762597289 762594874 0 0
T4 92416 92413 0 0
T7 2743 2740 0 0
T8 2538 2535 0 0
T9 3532 3529 0 0
T24 5023 5020 0 0
T25 4774 4771 0 0
T26 10020 10017 0 0
T27 3165 3162 0 0
T28 2259 2256 0 0
T29 1828 1825 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1835220171 1835217756 0 0
T4 356064 356061 0 0
T7 6741 6738 0 0
T8 6246 6243 0 0
T9 8652 8649 0 0
T24 12333 12330 0 0
T25 11469 11466 0 0
T26 24366 24363 0 0
T27 7542 7539 0 0
T28 5568 5565 0 0
T29 4461 4458 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 305187244 305186439 0 0
selKnown1 611740057 611739252 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 305187244 305186439 0 0
T4 36966 36965 0 0
T7 1097 1096 0 0
T8 1015 1014 0 0
T9 1429 1428 0 0
T24 2009 2008 0 0
T25 1935 1934 0 0
T26 4008 4007 0 0
T27 1313 1312 0 0
T28 905 904 0 0
T29 731 730 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 611740057 611739252 0 0
T4 118688 118687 0 0
T7 2247 2246 0 0
T8 2082 2081 0 0
T9 2884 2883 0 0
T24 4111 4110 0 0
T25 3823 3822 0 0
T26 8122 8121 0 0
T27 2514 2513 0 0
T28 1856 1855 0 0
T29 1487 1486 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10CoveredT9,T25,T27 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT9,T25,T27
11CoveredT9,T25,T27 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T25,T27
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 304817148 304816343 0 0
selKnown1 611740057 611739252 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 304817148 304816343 0 0
T4 36966 36965 0 0
T7 1097 1096 0 0
T8 1015 1014 0 0
T9 1388 1387 0 0
T24 2009 2008 0 0
T25 1872 1871 0 0
T26 4008 4007 0 0
T27 1197 1196 0 0
T28 902 901 0 0
T29 731 730 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 611740057 611739252 0 0
T4 118688 118687 0 0
T7 2247 2246 0 0
T8 2082 2081 0 0
T9 2884 2883 0 0
T24 4111 4110 0 0
T25 3823 3822 0 0
T26 8122 8121 0 0
T27 2514 2513 0 0
T28 1856 1855 0 0
T29 1487 1486 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 152592897 152592092 0 0
selKnown1 611740057 611739252 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 152592897 152592092 0 0
T4 18484 18483 0 0
T7 549 548 0 0
T8 508 507 0 0
T9 715 714 0 0
T24 1005 1004 0 0
T25 967 966 0 0
T26 2004 2003 0 0
T27 655 654 0 0
T28 452 451 0 0
T29 366 365 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 611740057 611739252 0 0
T4 118688 118687 0 0
T7 2247 2246 0 0
T8 2082 2081 0 0
T9 2884 2883 0 0
T24 4111 4110 0 0
T25 3823 3822 0 0
T26 8122 8121 0 0
T27 2514 2513 0 0
T28 1856 1855 0 0
T29 1487 1486 0 0

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