SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 349924890 | 345641424 | 0 | 0 |
gen_flops.OutputDelay_A | 349924890 | 345627032 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T24 | 2 | 2 | 0 | 0 |
T25 | 2 | 2 | 0 | 0 |
T26 | 2 | 2 | 0 | 0 |
T27 | 2 | 2 | 0 | 0 |
T28 | 2 | 2 | 0 | 0 |
T29 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 349924890 | 345641424 | 0 | 0 |
T4 | 34616 | 10654 | 0 | 0 |
T7 | 4636 | 4330 | 0 | 0 |
T8 | 4338 | 4028 | 0 | 0 |
T9 | 2944 | 2724 | 0 | 0 |
T24 | 4282 | 4142 | 0 | 0 |
T25 | 1674 | 1602 | 0 | 0 |
T26 | 1966 | 1910 | 0 | 0 |
T27 | 4138 | 3714 | 0 | 0 |
T28 | 1622 | 1540 | 0 | 0 |
T29 | 3090 | 2906 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 349924890 | 345627032 | 0 | 4830 |
T4 | 34616 | 10564 | 0 | 6 |
T7 | 4636 | 4324 | 0 | 6 |
T8 | 4338 | 4022 | 0 | 6 |
T9 | 2944 | 2718 | 0 | 6 |
T24 | 4282 | 4136 | 0 | 6 |
T25 | 1674 | 1596 | 0 | 6 |
T26 | 1966 | 1904 | 0 | 6 |
T27 | 4138 | 3708 | 0 | 6 |
T28 | 1622 | 1534 | 0 | 6 |
T29 | 3090 | 2900 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 174962445 | 172820712 | 0 | 0 |
gen_flops.OutputDelay_A | 174962445 | 172813516 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174962445 | 172820712 | 0 | 0 |
T4 | 17308 | 5327 | 0 | 0 |
T7 | 2318 | 2165 | 0 | 0 |
T8 | 2169 | 2014 | 0 | 0 |
T9 | 1472 | 1362 | 0 | 0 |
T24 | 2141 | 2071 | 0 | 0 |
T25 | 837 | 801 | 0 | 0 |
T26 | 983 | 955 | 0 | 0 |
T27 | 2069 | 1857 | 0 | 0 |
T28 | 811 | 770 | 0 | 0 |
T29 | 1545 | 1453 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174962445 | 172813516 | 0 | 2415 |
T4 | 17308 | 5282 | 0 | 3 |
T7 | 2318 | 2162 | 0 | 3 |
T8 | 2169 | 2011 | 0 | 3 |
T9 | 1472 | 1359 | 0 | 3 |
T24 | 2141 | 2068 | 0 | 3 |
T25 | 837 | 798 | 0 | 3 |
T26 | 983 | 952 | 0 | 3 |
T27 | 2069 | 1854 | 0 | 3 |
T28 | 811 | 767 | 0 | 3 |
T29 | 1545 | 1450 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 174962445 | 172820712 | 0 | 0 |
gen_flops.OutputDelay_A | 174962445 | 172813516 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174962445 | 172820712 | 0 | 0 |
T4 | 17308 | 5327 | 0 | 0 |
T7 | 2318 | 2165 | 0 | 0 |
T8 | 2169 | 2014 | 0 | 0 |
T9 | 1472 | 1362 | 0 | 0 |
T24 | 2141 | 2071 | 0 | 0 |
T25 | 837 | 801 | 0 | 0 |
T26 | 983 | 955 | 0 | 0 |
T27 | 2069 | 1857 | 0 | 0 |
T28 | 811 | 770 | 0 | 0 |
T29 | 1545 | 1453 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 174962445 | 172813516 | 0 | 2415 |
T4 | 17308 | 5282 | 0 | 3 |
T7 | 2318 | 2162 | 0 | 3 |
T8 | 2169 | 2011 | 0 | 3 |
T9 | 1472 | 1359 | 0 | 3 |
T24 | 2141 | 2068 | 0 | 3 |
T25 | 837 | 798 | 0 | 3 |
T26 | 983 | 952 | 0 | 3 |
T27 | 2069 | 1854 | 0 | 3 |
T28 | 811 | 767 | 0 | 3 |
T29 | 1545 | 1450 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |