Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	174962445	21582006	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	21582006	0	57
T1	260543	354960	0	0
T2	119820	25528	0	1
T3	139656	22580	0	0
T5	47579	0	0	0
T11	0	6724	0	1
T12	0	35769	0	0
T13	0	50376	0	1
T14	0	48359	0	0
T15	0	579589	0	0
T16	0	47552	0	0
T17	0	6595	0	1
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0
T35	0	0	0	1
T49	0	0	0	1
T111	0	0	0	1
T112	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1