Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	175787738	5693281	0	0
clk_enables_rd_A	175787738	51736	0	0
clk_hints_rd_A	175787738	44816	0	0
extclk_ctrl_rd_A	175787738	60148	0	0
extclk_ctrl_regwen_rd_A	175787738	45066	0	0
jitter_enable_rd_A	175787738	69324	0	0
jitter_regwen_rd_A	175787738	48536	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	5693281	0	0
T1	260543	120353	0	0
T2	119820	0	0	0
T3	139656	0	0	0
T5	47579	0	0	0
T15	0	165072	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0
T30	0	110110	0	0
T31	0	85275	0	0
T47	0	63320	0	0
T67	0	187448	0	0
T68	0	266882	0	0
T69	0	57442	0	0
T70	0	104732	0	0
T71	0	107797	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	51736	0	0
T4	17308	0	0	0
T6	74903	5	0	0
T8	2169	3	0	0
T9	1472	0	0	0
T12	0	3	0	0
T13	0	12	0	0
T14	0	16	0	0
T15	0	3339	0	0
T16	0	5	0	0
T19	0	1	0	0
T24	2141	0	0	0
T25	837	0	0	0
T26	983	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T30	0	4149	0	0
T73	0	3	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	44816	0	0
T2	119820	0	0	0
T3	139656	0	0	0
T5	47579	0	0	0
T12	0	5	0	0
T13	0	6	0	0
T14	0	13	0	0
T15	0	2906	0	0
T16	0	8	0	0
T19	2413	4	0	0
T20	923	0	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0
T30	0	3609	0	0
T73	0	1	0	0
T99	1587	0	0	0
T132	0	8	0	0
T133	0	6	0	0
T134	894	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	60148	0	0
T1	260543	0	0	0
T4	17308	0	0	0
T5	0	85	0	0
T6	74903	61	0	0
T9	1472	23	0	0
T12	0	71	0	0
T14	0	110	0	0
T21	0	41	0	0
T24	2141	0	0	0
T25	837	0	0	0
T26	983	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T73	0	28	0	0
T99	0	22	0	0
T115	0	19	0	0
T135	0	48	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	45066	0	0
T2	119820	0	0	0
T3	139656	0	0	0
T5	47579	44	0	0
T15	0	3033	0	0
T21	2536	0	0	0
T22	1488	0	0	0
T23	895	0	0	0
T30	0	3648	0	0
T32	177890	0	0	0
T42	1079	0	0	0
T47	0	1099	0	0
T70	0	1637	0	0
T71	0	1849	0	0
T75	0	3	0	0
T99	1587	0	0	0
T134	894	0	0	0
T136	0	2	0	0
T137	0	76	0	0
T138	0	3355	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	69324	0	0
T4	17308	0	0	0
T6	74903	144	0	0
T8	2169	97	0	0
T9	1472	0	0	0
T12	0	131	0	0
T13	0	445	0	0
T14	0	345	0	0
T15	0	4055	0	0
T16	0	246	0	0
T19	0	135	0	0
T24	2141	0	0	0
T25	837	0	0	0
T26	983	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T30	0	6041	0	0
T73	0	113	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	48536	0	0
T15	547672	3155	0	0
T30	0	4105	0	0
T47	0	1091	0	0
T70	0	1924	0	0
T71	0	1946	0	0
T138	0	3481	0	0
T139	0	2398	0	0
T140	0	967	0	0
T141	0	2055	0	0
T142	0	2685	0	0
T143	26139	0	0	0
T144	1605	0	0	0
T145	1058	0	0	0
T146	3181	0	0	0
T147	1032	0	0	0
T148	3475	0	0	0
T149	1552	0	0	0
T150	1495	0	0	0
T151	805	0	0	0