Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 3 | 50.00 |
Logical | 6 | 3 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
26099000 |
0 |
0 |
T1 |
1302715 |
92 |
0 |
0 |
T2 |
479280 |
8 |
0 |
0 |
T3 |
558624 |
28 |
0 |
0 |
T4 |
315083 |
25 |
0 |
0 |
T5 |
237895 |
0 |
0 |
0 |
T6 |
74903 |
0 |
0 |
0 |
T7 |
6234 |
35 |
0 |
0 |
T8 |
5774 |
30 |
0 |
0 |
T9 |
8032 |
43 |
0 |
0 |
T11 |
0 |
18 |
0 |
0 |
T13 |
0 |
41 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T15 |
0 |
210 |
0 |
0 |
T16 |
0 |
37 |
0 |
0 |
T17 |
0 |
14 |
0 |
0 |
T18 |
6165 |
0 |
0 |
0 |
T19 |
12065 |
0 |
0 |
0 |
T20 |
4615 |
0 |
0 |
0 |
T21 |
10144 |
0 |
0 |
0 |
T22 |
5952 |
0 |
0 |
0 |
T23 |
3580 |
0 |
0 |
0 |
T24 |
11408 |
64 |
0 |
0 |
T25 |
10708 |
59 |
0 |
0 |
T26 |
21230 |
127 |
0 |
0 |
T27 |
9170 |
38 |
0 |
0 |
T28 |
5957 |
30 |
0 |
0 |
T29 |
5669 |
24 |
0 |
0 |
T30 |
0 |
130 |
0 |
0 |
T31 |
0 |
41 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
158179 |
0 |
0 |
T1 |
3994152 |
2680 |
0 |
0 |
T2 |
556732 |
186 |
0 |
0 |
T3 |
1751926 |
528 |
0 |
0 |
T4 |
357121 |
126 |
0 |
0 |
T5 |
549432 |
136 |
0 |
0 |
T6 |
857821 |
190 |
0 |
0 |
T11 |
0 |
187 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
115 |
0 |
0 |
T14 |
0 |
33 |
0 |
0 |
T15 |
0 |
459 |
0 |
0 |
T16 |
0 |
74 |
0 |
0 |
T17 |
0 |
22 |
0 |
0 |
T18 |
72124 |
0 |
0 |
0 |
T19 |
15536 |
0 |
0 |
0 |
T20 |
26432 |
0 |
0 |
0 |
T21 |
8139 |
0 |
0 |
0 |
T22 |
18717 |
0 |
0 |
0 |
T23 |
11269 |
0 |
0 |
0 |
T27 |
8358 |
0 |
0 |
0 |
T28 |
6073 |
0 |
0 |
0 |
T29 |
4857 |
0 |
0 |
0 |
T30 |
0 |
215 |
0 |
0 |
T31 |
0 |
71 |
0 |
0 |
T32 |
0 |
150 |
0 |
0 |
T33 |
0 |
30 |
0 |
0 |
T34 |
0 |
40 |
0 |
0 |
T35 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
611740057 |
5233638 |
0 |
0 |
T4 |
118688 |
25 |
0 |
0 |
T7 |
2247 |
35 |
0 |
0 |
T8 |
2082 |
30 |
0 |
0 |
T9 |
2884 |
43 |
0 |
0 |
T24 |
4111 |
64 |
0 |
0 |
T25 |
3823 |
59 |
0 |
0 |
T26 |
8122 |
127 |
0 |
0 |
T27 |
2514 |
38 |
0 |
0 |
T28 |
1856 |
30 |
0 |
0 |
T29 |
1487 |
24 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23605627 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305187244 |
5233527 |
0 |
0 |
T4 |
36966 |
25 |
0 |
0 |
T7 |
1097 |
35 |
0 |
0 |
T8 |
1015 |
30 |
0 |
0 |
T9 |
1429 |
43 |
0 |
0 |
T24 |
2009 |
64 |
0 |
0 |
T25 |
1935 |
59 |
0 |
0 |
T26 |
4008 |
127 |
0 |
0 |
T27 |
1313 |
38 |
0 |
0 |
T28 |
905 |
30 |
0 |
0 |
T29 |
731 |
24 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23605627 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152592897 |
4990567 |
0 |
0 |
T4 |
18484 |
24 |
0 |
0 |
T7 |
549 |
32 |
0 |
0 |
T8 |
508 |
29 |
0 |
0 |
T9 |
715 |
41 |
0 |
0 |
T24 |
1005 |
61 |
0 |
0 |
T25 |
967 |
56 |
0 |
0 |
T26 |
2004 |
120 |
0 |
0 |
T27 |
655 |
37 |
0 |
0 |
T28 |
452 |
28 |
0 |
0 |
T29 |
366 |
22 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23605627 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
5238224 |
0 |
0 |
T4 |
123637 |
25 |
0 |
0 |
T7 |
2341 |
35 |
0 |
0 |
T8 |
2169 |
30 |
0 |
0 |
T9 |
3004 |
43 |
0 |
0 |
T24 |
4283 |
64 |
0 |
0 |
T25 |
3983 |
59 |
0 |
0 |
T26 |
7096 |
106 |
0 |
0 |
T27 |
2619 |
38 |
0 |
0 |
T28 |
1933 |
30 |
0 |
0 |
T29 |
1540 |
24 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23605627 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T7,T8,T9 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T7,T8,T9 |
EVEN |
0 |
- |
Covered |
T7,T8,T9 |
ODD |
- |
1 |
Covered |
T7,T8,T9 |
ODD |
- |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
311933295 |
5238350 |
0 |
0 |
T4 |
59346 |
25 |
0 |
0 |
T7 |
1124 |
35 |
0 |
0 |
T8 |
1041 |
30 |
0 |
0 |
T9 |
1442 |
43 |
0 |
0 |
T24 |
2055 |
64 |
0 |
0 |
T25 |
1912 |
59 |
0 |
0 |
T26 |
3633 |
114 |
0 |
0 |
T27 |
1257 |
38 |
0 |
0 |
T28 |
927 |
30 |
0 |
0 |
T29 |
733 |
23 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23605627 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T1 |
1 | 1 | Covered | T4,T6,T1 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T4,T6,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T4,T6,T1 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T4,T6,T1 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175787738 |
29510 |
0 |
0 |
T1 |
260543 |
501 |
0 |
0 |
T2 |
0 |
33 |
0 |
0 |
T3 |
0 |
99 |
0 |
0 |
T4 |
17308 |
28 |
0 |
0 |
T5 |
47579 |
30 |
0 |
0 |
T6 |
74903 |
38 |
0 |
0 |
T11 |
0 |
32 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T27 |
2069 |
0 |
0 |
0 |
T28 |
811 |
0 |
0 |
0 |
T29 |
1545 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
614168669 |
28220 |
0 |
0 |
T1 |
597636 |
478 |
0 |
0 |
T2 |
0 |
30 |
0 |
0 |
T3 |
0 |
92 |
0 |
0 |
T4 |
118688 |
28 |
0 |
0 |
T5 |
93213 |
30 |
0 |
0 |
T6 |
236252 |
38 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T18 |
10761 |
0 |
0 |
0 |
T19 |
2387 |
0 |
0 |
0 |
T20 |
4033 |
0 |
0 |
0 |
T27 |
2514 |
0 |
0 |
0 |
T28 |
1856 |
0 |
0 |
0 |
T29 |
1487 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T1 |
1 | 1 | Covered | T4,T6,T1 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T4,T6,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T4,T6,T1 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T4,T6,T1 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175787738 |
29510 |
0 |
0 |
T1 |
260543 |
501 |
0 |
0 |
T2 |
0 |
33 |
0 |
0 |
T3 |
0 |
99 |
0 |
0 |
T4 |
17308 |
28 |
0 |
0 |
T5 |
47579 |
30 |
0 |
0 |
T6 |
74903 |
38 |
0 |
0 |
T11 |
0 |
32 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T27 |
2069 |
0 |
0 |
0 |
T28 |
811 |
0 |
0 |
0 |
T29 |
1545 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
306355772 |
28218 |
0 |
0 |
T1 |
298557 |
478 |
0 |
0 |
T2 |
0 |
30 |
0 |
0 |
T3 |
0 |
92 |
0 |
0 |
T4 |
36966 |
28 |
0 |
0 |
T5 |
25196 |
30 |
0 |
0 |
T6 |
118437 |
38 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T18 |
5807 |
0 |
0 |
0 |
T19 |
1133 |
0 |
0 |
0 |
T20 |
1977 |
0 |
0 |
0 |
T27 |
1313 |
0 |
0 |
0 |
T28 |
905 |
0 |
0 |
0 |
T29 |
731 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T1 |
1 | 1 | Covered | T4,T6,T1 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T4,T6,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T4,T6,T1 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T4,T6,T1 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175787738 |
29510 |
0 |
0 |
T1 |
260543 |
501 |
0 |
0 |
T2 |
0 |
33 |
0 |
0 |
T3 |
0 |
99 |
0 |
0 |
T4 |
17308 |
28 |
0 |
0 |
T5 |
47579 |
30 |
0 |
0 |
T6 |
74903 |
38 |
0 |
0 |
T11 |
0 |
32 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T27 |
2069 |
0 |
0 |
0 |
T28 |
811 |
0 |
0 |
0 |
T29 |
1545 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
153177175 |
28205 |
0 |
0 |
T1 |
149277 |
478 |
0 |
0 |
T2 |
0 |
30 |
0 |
0 |
T3 |
0 |
92 |
0 |
0 |
T4 |
18484 |
28 |
0 |
0 |
T5 |
12599 |
30 |
0 |
0 |
T6 |
59217 |
38 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T18 |
2903 |
0 |
0 |
0 |
T19 |
567 |
0 |
0 |
0 |
T20 |
988 |
0 |
0 |
0 |
T27 |
655 |
0 |
0 |
0 |
T28 |
452 |
0 |
0 |
0 |
T29 |
366 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T1 |
1 | 1 | Covered | T4,T6,T1 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T4,T6,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T4,T6,T1 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T4,T6,T1 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175787738 |
29510 |
0 |
0 |
T1 |
260543 |
501 |
0 |
0 |
T2 |
0 |
33 |
0 |
0 |
T3 |
0 |
99 |
0 |
0 |
T4 |
17308 |
28 |
0 |
0 |
T5 |
47579 |
30 |
0 |
0 |
T6 |
74903 |
38 |
0 |
0 |
T11 |
0 |
32 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T27 |
2069 |
0 |
0 |
0 |
T28 |
811 |
0 |
0 |
0 |
T29 |
1545 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
651847961 |
28220 |
0 |
0 |
T1 |
643558 |
478 |
0 |
0 |
T2 |
0 |
30 |
0 |
0 |
T3 |
0 |
92 |
0 |
0 |
T4 |
123637 |
28 |
0 |
0 |
T5 |
97100 |
30 |
0 |
0 |
T6 |
294103 |
38 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T18 |
11210 |
0 |
0 |
0 |
T19 |
2487 |
0 |
0 |
0 |
T20 |
4201 |
0 |
0 |
0 |
T27 |
2619 |
0 |
0 |
0 |
T28 |
1933 |
0 |
0 |
0 |
T29 |
1540 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T1 |
1 | 1 | Covered | T4,T6,T1 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T4,T6,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T6,T1,T5 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T4,T6,T1 |
EVEN |
0 |
- |
Covered |
T4,T6,T1 |
ODD |
- |
1 |
Covered |
T6,T1,T5 |
ODD |
- |
0 |
Covered |
T4,T6,T1 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175787738 |
29034 |
0 |
0 |
T1 |
260543 |
501 |
0 |
0 |
T2 |
0 |
33 |
0 |
0 |
T3 |
0 |
99 |
0 |
0 |
T4 |
17308 |
14 |
0 |
0 |
T5 |
47579 |
18 |
0 |
0 |
T6 |
74903 |
38 |
0 |
0 |
T11 |
0 |
32 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T27 |
2069 |
0 |
0 |
0 |
T28 |
811 |
0 |
0 |
0 |
T29 |
1545 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
313147621 |
27696 |
0 |
0 |
T1 |
308048 |
478 |
0 |
0 |
T2 |
0 |
30 |
0 |
0 |
T3 |
0 |
92 |
0 |
0 |
T4 |
59346 |
14 |
0 |
0 |
T5 |
46608 |
16 |
0 |
0 |
T6 |
149812 |
38 |
0 |
0 |
T11 |
0 |
30 |
0 |
0 |
T18 |
5381 |
0 |
0 |
0 |
T19 |
1194 |
0 |
0 |
0 |
T20 |
2017 |
0 |
0 |
0 |
T27 |
1257 |
0 |
0 |
0 |
T28 |
927 |
0 |
0 |
0 |
T29 |
733 |
0 |
0 |
0 |
T32 |
0 |
30 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T34 |
0 |
8 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
3652 |
0 |
0 |
T1 |
260543 |
47 |
0 |
0 |
T2 |
119820 |
11 |
0 |
0 |
T3 |
139656 |
7 |
0 |
0 |
T5 |
47579 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
29 |
0 |
0 |
T14 |
0 |
11 |
0 |
0 |
T15 |
0 |
62 |
0 |
0 |
T16 |
0 |
29 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T21 |
2536 |
0 |
0 |
0 |
T22 |
1488 |
0 |
0 |
0 |
T23 |
895 |
0 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
611740057 |
3652 |
0 |
0 |
T1 |
597636 |
47 |
0 |
0 |
T2 |
169155 |
11 |
0 |
0 |
T3 |
512537 |
7 |
0 |
0 |
T5 |
93213 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
T13 |
0 |
29 |
0 |
0 |
T14 |
0 |
11 |
0 |
0 |
T15 |
0 |
62 |
0 |
0 |
T16 |
0 |
29 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
10761 |
0 |
0 |
0 |
T19 |
2387 |
0 |
0 |
0 |
T20 |
4033 |
0 |
0 |
0 |
T21 |
2435 |
0 |
0 |
0 |
T22 |
5717 |
0 |
0 |
0 |
T23 |
3442 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
3630 |
0 |
0 |
T1 |
260543 |
47 |
0 |
0 |
T2 |
119820 |
4 |
0 |
0 |
T3 |
139656 |
13 |
0 |
0 |
T5 |
47579 |
0 |
0 |
0 |
T11 |
0 |
11 |
0 |
0 |
T13 |
0 |
22 |
0 |
0 |
T15 |
0 |
91 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T17 |
0 |
10 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T21 |
2536 |
0 |
0 |
0 |
T22 |
1488 |
0 |
0 |
0 |
T23 |
895 |
0 |
0 |
0 |
T30 |
0 |
53 |
0 |
0 |
T31 |
0 |
41 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
305187244 |
3630 |
0 |
0 |
T1 |
298557 |
47 |
0 |
0 |
T2 |
84524 |
4 |
0 |
0 |
T3 |
256105 |
13 |
0 |
0 |
T5 |
25196 |
0 |
0 |
0 |
T11 |
0 |
11 |
0 |
0 |
T13 |
0 |
22 |
0 |
0 |
T15 |
0 |
91 |
0 |
0 |
T16 |
0 |
19 |
0 |
0 |
T17 |
0 |
10 |
0 |
0 |
T18 |
5807 |
0 |
0 |
0 |
T19 |
1133 |
0 |
0 |
0 |
T20 |
1977 |
0 |
0 |
0 |
T21 |
1303 |
0 |
0 |
0 |
T22 |
2791 |
0 |
0 |
0 |
T23 |
1681 |
0 |
0 |
0 |
T30 |
0 |
53 |
0 |
0 |
T31 |
0 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
3501 |
0 |
0 |
T1 |
260543 |
45 |
0 |
0 |
T2 |
119820 |
4 |
0 |
0 |
T3 |
139656 |
15 |
0 |
0 |
T5 |
47579 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T13 |
0 |
19 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T15 |
0 |
119 |
0 |
0 |
T16 |
0 |
18 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T21 |
2536 |
0 |
0 |
0 |
T22 |
1488 |
0 |
0 |
0 |
T23 |
895 |
0 |
0 |
0 |
T30 |
0 |
77 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
152592897 |
3501 |
0 |
0 |
T1 |
149277 |
45 |
0 |
0 |
T2 |
42262 |
4 |
0 |
0 |
T3 |
128053 |
15 |
0 |
0 |
T5 |
12599 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T13 |
0 |
19 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T15 |
0 |
119 |
0 |
0 |
T16 |
0 |
18 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
2903 |
0 |
0 |
0 |
T19 |
567 |
0 |
0 |
0 |
T20 |
988 |
0 |
0 |
0 |
T21 |
648 |
0 |
0 |
0 |
T22 |
1396 |
0 |
0 |
0 |
T23 |
841 |
0 |
0 |
0 |
T30 |
0 |
77 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
3470 |
0 |
0 |
T1 |
260543 |
72 |
0 |
0 |
T2 |
119820 |
14 |
0 |
0 |
T3 |
139656 |
7 |
0 |
0 |
T5 |
47579 |
0 |
0 |
0 |
T11 |
0 |
8 |
0 |
0 |
T13 |
0 |
19 |
0 |
0 |
T14 |
0 |
11 |
0 |
0 |
T15 |
0 |
100 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T21 |
2536 |
0 |
0 |
0 |
T22 |
1488 |
0 |
0 |
0 |
T23 |
895 |
0 |
0 |
0 |
T30 |
0 |
42 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
649318036 |
3470 |
0 |
0 |
T1 |
643558 |
72 |
0 |
0 |
T2 |
176209 |
14 |
0 |
0 |
T3 |
575910 |
7 |
0 |
0 |
T5 |
97100 |
0 |
0 |
0 |
T11 |
0 |
8 |
0 |
0 |
T13 |
0 |
19 |
0 |
0 |
T14 |
0 |
11 |
0 |
0 |
T15 |
0 |
100 |
0 |
0 |
T16 |
0 |
8 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
11210 |
0 |
0 |
0 |
T19 |
2487 |
0 |
0 |
0 |
T20 |
4201 |
0 |
0 |
0 |
T21 |
2536 |
0 |
0 |
0 |
T22 |
5955 |
0 |
0 |
0 |
T23 |
3585 |
0 |
0 |
0 |
T30 |
0 |
42 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_err_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174962445 |
3367 |
0 |
0 |
T1 |
260543 |
79 |
0 |
0 |
T2 |
119820 |
3 |
0 |
0 |
T3 |
139656 |
26 |
0 |
0 |
T5 |
47579 |
0 |
0 |
0 |
T11 |
0 |
8 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
7 |
0 |
0 |
T15 |
0 |
87 |
0 |
0 |
T18 |
1233 |
0 |
0 |
0 |
T19 |
2413 |
0 |
0 |
0 |
T20 |
923 |
0 |
0 |
0 |
T21 |
2536 |
0 |
0 |
0 |
T22 |
1488 |
0 |
0 |
0 |
T23 |
895 |
0 |
0 |
0 |
T30 |
0 |
43 |
0 |
0 |
T31 |
0 |
30 |
0 |
0 |
T35 |
0 |
16 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
311933295 |
3367 |
0 |
0 |
T1 |
308048 |
79 |
0 |
0 |
T2 |
84582 |
3 |
0 |
0 |
T3 |
279321 |
26 |
0 |
0 |
T5 |
46608 |
0 |
0 |
0 |
T11 |
0 |
8 |
0 |
0 |
T13 |
0 |
26 |
0 |
0 |
T14 |
0 |
7 |
0 |
0 |
T15 |
0 |
87 |
0 |
0 |
T18 |
5381 |
0 |
0 |
0 |
T19 |
1194 |
0 |
0 |
0 |
T20 |
2017 |
0 |
0 |
0 |
T21 |
1217 |
0 |
0 |
0 |
T22 |
2858 |
0 |
0 |
0 |
T23 |
1720 |
0 |
0 |
0 |
T30 |
0 |
43 |
0 |
0 |
T31 |
0 |
30 |
0 |
0 |
T35 |
0 |
16 |
0 |
0 |