Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1757877380	1491910	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1757877380	308034	0	0
SrcBusyKnown_A	1757877380	1735416060	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1757877380	1491910	0	0
T1	2605430	22125	0	0
T2	0	1851	0	0
T3	0	3279	0	0
T4	173080	1124	0	0
T5	475790	2276	0	0
T6	749030	1328	0	0
T11	0	996	0	0
T18	12330	0	0	0
T19	24130	0	0	0
T20	9230	0	0	0
T27	20690	0	0	0
T28	8110	0	0	0
T29	15450	0	0	0
T32	0	2387	0	0
T33	0	442	0	0
T34	0	410	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	714242	239866	0	0
T7	14716	13816	0	0
T8	13630	12732	0	0
T9	18948	17678	0	0
T24	26926	26180	0	0
T25	25240	24292	0	0
T26	49726	48280	0	0
T27	16716	15198	0	0
T28	12146	11608	0	0
T29	9714	9136	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1757877380	308034	0	0
T1	2605430	4830	0	0
T2	0	300	0	0
T3	0	920	0	0
T4	173080	406	0	0
T5	475790	436	0	0
T6	749030	380	0	0
T11	0	300	0	0
T18	12330	0	0	0
T19	24130	0	0	0
T20	9230	0	0	0
T27	20690	0	0	0
T28	8110	0	0	0
T29	15450	0	0	0
T32	0	300	0	0
T33	0	60	0	0
T34	0	80	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1757877380	1735416060	0	0
T4	173080	53270	0	0
T7	23180	21650	0	0
T8	21690	20140	0	0
T9	14720	13620	0	0
T24	21410	20710	0	0
T25	8370	8010	0	0
T26	9830	9550	0	0
T27	20690	18570	0	0
T28	8110	7700	0	0
T29	15450	14530	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	95315	0	0
DstReqKnown_A	614168669	609696350	0	0
SrcAckBusyChk_A	175787738	28220	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	95315	0	0
T1	260543	1609	0	0
T2	0	121	0	0
T3	0	242	0	0
T4	17308	67	0	0
T5	47579	110	0	0
T6	74903	98	0	0
T11	0	73	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	146	0	0
T33	0	26	0	0
T34	0	28	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614168669	609696350	0	0
T4	118688	36433	0	0
T7	2247	2098	0	0
T8	2082	1934	0	0
T9	2884	2667	0	0
T24	4111	3977	0	0
T25	3823	3661	0	0
T26	8122	7878	0	0
T27	2514	2256	0	0
T28	1856	1762	0	0
T29	1487	1394	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	28220	0	0
T1	260543	478	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	28	0	0
T5	47579	30	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	135747	0	0
DstReqKnown_A	306355772	305218333	0	0
SrcAckBusyChk_A	175787738	28220	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	135747	0	0
T1	260543	2207	0	0
T2	0	185	0	0
T3	0	334	0	0
T4	17308	71	0	0
T5	47579	158	0	0
T6	74903	136	0	0
T11	0	103	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	238	0	0
T33	0	45	0	0
T34	0	40	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306355772	305218333	0	0
T4	36966	18218	0	0
T7	1097	1049	0	0
T8	1015	967	0	0
T9	1429	1374	0	0
T24	2009	1988	0	0
T25	1935	1894	0	0
T26	4008	3939	0	0
T27	1313	1244	0	0
T28	905	884	0	0
T29	731	697	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	28220	0	0
T1	260543	478	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	28	0	0
T5	47579	30	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	214996	0	0
DstReqKnown_A	153177175	152608569	0	0
SrcAckBusyChk_A	175787738	28220	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	214996	0	0
T1	260543	3410	0	0
T2	0	315	0	0
T3	0	485	0	0
T4	17308	101	0	0
T5	47579	253	0	0
T6	74903	196	0	0
T11	0	146	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	421	0	0
T33	0	76	0	0
T34	0	69	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153177175	152608569	0	0
T4	18484	9110	0	0
T7	549	525	0	0
T8	508	484	0	0
T9	715	688	0	0
T24	1005	995	0	0
T25	967	946	0	0
T26	2004	1970	0	0
T27	655	621	0	0
T28	452	442	0	0
T29	366	349	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	28220	0	0
T1	260543	478	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	28	0	0
T5	47579	30	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	96909	0	0
DstReqKnown_A	651847961	647127411	0	0
SrcAckBusyChk_A	175787738	28220	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	96909	0	0
T1	260543	1557	0	0
T2	0	119	0	0
T3	0	242	0	0
T4	17308	67	0	0
T5	47579	107	0	0
T6	74903	98	0	0
T11	0	73	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	144	0	0
T33	0	32	0	0
T34	0	28	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651847961	647127411	0	0
T4	123637	37954	0	0
T7	2341	2186	0	0
T8	2169	2014	0	0
T9	3004	2777	0	0
T24	4283	4142	0	0
T25	3983	3814	0	0
T26	7096	6842	0	0
T27	2619	2350	0	0
T28	1933	1835	0	0
T29	1540	1442	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	28220	0	0
T1	260543	478	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	28	0	0
T5	47579	30	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	134775	0	0
DstReqKnown_A	313147621	310876837	0	0
SrcAckBusyChk_A	175787738	27744	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	134775	0	0
T1	260543	2202	0	0
T2	0	187	0	0
T3	0	334	0	0
T4	17308	50	0	0
T5	47579	109	0	0
T6	74903	136	0	0
T11	0	103	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	235	0	0
T33	0	41	0	0
T34	0	40	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313147621	310876837	0	0
T4	59346	18218	0	0
T7	1124	1050	0	0
T8	1041	967	0	0
T9	1442	1333	0	0
T24	2055	1988	0	0
T25	1912	1831	0	0
T26	3633	3511	0	0
T27	1257	1128	0	0
T28	927	881	0	0
T29	733	686	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	27744	0	0
T1	260543	478	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	14	0	0
T5	47579	18	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	114291	0	0
DstReqKnown_A	614168669	609696350	0	0
SrcAckBusyChk_A	175787738	33560	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	114291	0	0
T1	260543	1652	0	0
T2	0	121	0	0
T3	0	243	0	0
T4	17308	134	0	0
T5	47579	215	0	0
T6	74903	98	0	0
T11	0	73	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	150	0	0
T33	0	27	0	0
T34	0	29	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614168669	609696350	0	0
T4	118688	36433	0	0
T7	2247	2098	0	0
T8	2082	1934	0	0
T9	2884	2667	0	0
T24	4111	3977	0	0
T25	3823	3661	0	0
T26	8122	7878	0	0
T27	2514	2256	0	0
T28	1856	1762	0	0
T29	1487	1394	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	33560	0	0
T1	260543	488	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	56	0	0
T5	47579	60	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	162694	0	0
DstReqKnown_A	306355772	305218333	0	0
SrcAckBusyChk_A	175787738	33466	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	162694	0	0
T1	260543	2227	0	0
T2	0	186	0	0
T3	0	335	0	0
T4	17308	148	0	0
T5	47579	308	0	0
T6	74903	136	0	0
T11	0	103	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	240	0	0
T33	0	46	0	0
T34	0	40	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	306355772	305218333	0	0
T4	36966	18218	0	0
T7	1097	1049	0	0
T8	1015	967	0	0
T9	1429	1374	0	0
T24	2009	1988	0	0
T25	1935	1894	0	0
T26	4008	3939	0	0
T27	1313	1244	0	0
T28	905	884	0	0
T29	731	697	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	33466	0	0
T1	260543	488	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	56	0	0
T5	47579	60	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	258356	0	0
DstReqKnown_A	153177175	152608569	0	0
SrcAckBusyChk_A	175787738	33516	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	258356	0	0
T1	260543	3463	0	0
T2	0	310	0	0
T3	0	486	0	0
T4	17308	205	0	0
T5	47579	494	0	0
T6	74903	196	0	0
T11	0	146	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	429	0	0
T33	0	76	0	0
T34	0	68	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153177175	152608569	0	0
T4	18484	9110	0	0
T7	549	525	0	0
T8	508	484	0	0
T9	715	688	0	0
T24	1005	995	0	0
T25	967	946	0	0
T26	2004	1970	0	0
T27	655	621	0	0
T28	452	442	0	0
T29	366	349	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	33516	0	0
T1	260543	488	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	56	0	0
T5	47579	60	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	115180	0	0
DstReqKnown_A	651847961	647127411	0	0
SrcAckBusyChk_A	175787738	33418	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	115180	0	0
T1	260543	1607	0	0
T2	0	119	0	0
T3	0	243	0	0
T4	17308	134	0	0
T5	47579	212	0	0
T6	74903	98	0	0
T11	0	73	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	144	0	0
T33	0	32	0	0
T34	0	28	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651847961	647127411	0	0
T4	123637	37954	0	0
T7	2341	2186	0	0
T8	2169	2014	0	0
T9	3004	2777	0	0
T24	4283	4142	0	0
T25	3983	3814	0	0
T26	7096	6842	0	0
T27	2619	2350	0	0
T28	1933	1835	0	0
T29	1540	1442	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	33418	0	0
T1	260543	488	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	56	0	0
T5	47579	60	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T6,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T4,T6,T1
0	0	0	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	175787738	163647	0	0
DstReqKnown_A	313147621	310876837	0	0
SrcAckBusyChk_A	175787738	33450	0	0
SrcBusyKnown_A	175787738	173541606	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	163647	0	0
T1	260543	2191	0	0
T2	0	188	0	0
T3	0	335	0	0
T4	17308	147	0	0
T5	47579	310	0	0
T6	74903	136	0	0
T11	0	103	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	240	0	0
T33	0	41	0	0
T34	0	40	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313147621	310876837	0	0
T4	59346	18218	0	0
T7	1124	1050	0	0
T8	1041	967	0	0
T9	1442	1333	0	0
T24	2055	1988	0	0
T25	1912	1831	0	0
T26	3633	3511	0	0
T27	1257	1128	0	0
T28	927	881	0	0
T29	733	686	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	33450	0	0
T1	260543	488	0	0
T2	0	30	0	0
T3	0	92	0	0
T4	17308	56	0	0
T5	47579	58	0	0
T6	74903	38	0	0
T11	0	30	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	0	0	0
T32	0	30	0	0
T33	0	6	0	0
T34	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175787738	173541606	0	0
T4	17308	5327	0	0
T7	2318	2165	0	0
T8	2169	2014	0	0
T9	1472	1362	0	0
T24	2141	2071	0	0
T25	837	801	0	0
T26	983	955	0	0
T27	2069	1857	0	0
T28	811	770	0	0
T29	1545	1453	0	0