Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T27,T6,T1
1	1	Covered	T9,T25,T27

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	611740454	5208	0	0
g_div2.Div2Whole_A	611740454	6046	0	0
g_div4.Div4Stepped_A	305187637	5097	0	0
g_div4.Div4Whole_A	305187637	5763	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740454	5208	0	0
T1	597636	98	0	0
T3	0	2	0	0
T4	118689	0	0	0
T6	236252	12	0	0
T9	2884	1	0	0
T18	0	4	0	0
T21	0	7	0	0
T24	4111	0	0	0
T25	3824	1	0	0
T26	8123	0	0	0
T27	2514	7	0	0
T28	1856	0	0	0
T29	1487	0	0	0
T99	0	7	0	0
T135	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740454	6046	0	0
T1	597636	115	0	0
T3	0	2	0	0
T4	118689	0	0	0
T6	236252	14	0	0
T9	2884	2	0	0
T18	0	4	0	0
T21	0	11	0	0
T24	4111	0	0	0
T25	3824	1	0	0
T26	8123	0	0	0
T27	2514	8	0	0
T28	1856	1	0	0
T29	1487	0	0	0
T99	0	7	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187637	5097	0	0
T1	298557	96	0	0
T3	0	2	0	0
T4	36966	0	0	0
T6	118437	12	0	0
T9	1430	1	0	0
T18	0	4	0	0
T21	0	6	0	0
T24	2010	0	0	0
T25	1935	1	0	0
T26	4008	0	0	0
T27	1313	7	0	0
T28	905	0	0	0
T29	732	0	0	0
T99	0	7	0	0
T135	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187637	5763	0	0
T1	298557	113	0	0
T3	0	2	0	0
T4	36966	0	0	0
T6	118437	14	0	0
T9	1430	2	0	0
T18	0	4	0	0
T21	0	9	0	0
T24	2010	0	0	0
T25	1935	1	0	0
T26	4008	0	0	0
T27	1313	8	0	0
T28	905	1	0	0
T29	732	0	0	0
T99	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T27,T6,T1
1	1	Covered	T9,T25,T27

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	611740454	5208	0	0
g_div2.Div2Whole_A	611740454	6046	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740454	5208	0	0
T1	597636	98	0	0
T3	0	2	0	0
T4	118689	0	0	0
T6	236252	12	0	0
T9	2884	1	0	0
T18	0	4	0	0
T21	0	7	0	0
T24	4111	0	0	0
T25	3824	1	0	0
T26	8123	0	0	0
T27	2514	7	0	0
T28	1856	0	0	0
T29	1487	0	0	0
T99	0	7	0	0
T135	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740454	6046	0	0
T1	597636	115	0	0
T3	0	2	0	0
T4	118689	0	0	0
T6	236252	14	0	0
T9	2884	2	0	0
T18	0	4	0	0
T21	0	11	0	0
T24	4111	0	0	0
T25	3824	1	0	0
T26	8123	0	0	0
T27	2514	8	0	0
T28	1856	1	0	0
T29	1487	0	0	0
T99	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T27,T6,T1
1	1	Covered	T9,T25,T27

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	305187637	5097	0	0
g_div4.Div4Whole_A	305187637	5763	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187637	5097	0	0
T1	298557	96	0	0
T3	0	2	0	0
T4	36966	0	0	0
T6	118437	12	0	0
T9	1430	1	0	0
T18	0	4	0	0
T21	0	6	0	0
T24	2010	0	0	0
T25	1935	1	0	0
T26	4008	0	0	0
T27	1313	7	0	0
T28	905	0	0	0
T29	732	0	0	0
T99	0	7	0	0
T135	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187637	5763	0	0
T1	298557	113	0	0
T3	0	2	0	0
T4	36966	0	0	0
T6	118437	14	0	0
T9	1430	2	0	0
T18	0	4	0	0
T21	0	9	0	0
T24	2010	0	0	0
T25	1935	1	0	0
T26	4008	0	0	0
T27	1313	8	0	0
T28	905	1	0	0
T29	732	0	0	0
T99	0	7	0	0