Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	524887335	402	0	0
StatusRise_A	524887335	402	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524887335	402	0	0
T1	781629	0	0	0
T4	51924	0	0	0
T6	224709	0	0	0
T18	3699	0	0	0
T19	7239	0	0	0
T20	2769	0	0	0
T26	2949	10	0	0
T27	6207	0	0	0
T28	2433	0	0	0
T29	4635	9	0	0
T42	0	2	0	0
T43	0	12	0	0
T152	0	6	0	0
T153	0	4	0	0
T154	0	12	0	0
T155	0	12	0	0
T156	0	15	0	0
T157	0	6	0	0
T158	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524887335	402	0	0
T1	781629	0	0	0
T4	51924	0	0	0
T6	224709	0	0	0
T18	3699	0	0	0
T19	7239	0	0	0
T20	2769	0	0	0
T26	2949	10	0	0
T27	6207	0	0	0
T28	2433	0	0	0
T29	4635	9	0	0
T42	0	2	0	0
T43	0	12	0	0
T152	0	6	0	0
T153	0	4	0	0
T154	0	12	0	0
T155	0	12	0	0
T156	0	15	0	0
T157	0	6	0	0
T158	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	174962445	127	0	0
StatusRise_A	174962445	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	127	0	0
T1	260543	0	0	0
T4	17308	0	0	0
T6	74903	0	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T26	983	3	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	2	0	0
T42	0	1	0	0
T43	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	127	0	0
T1	260543	0	0	0
T4	17308	0	0	0
T6	74903	0	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T26	983	3	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	2	0	0
T42	0	1	0	0
T43	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	5	0	0
T157	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	174962445	141	0	0
StatusRise_A	174962445	141	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	141	0	0
T1	260543	0	0	0
T4	17308	0	0	0
T6	74903	0	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T26	983	4	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	141	0	0
T1	260543	0	0	0
T4	17308	0	0	0
T6	74903	0	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T26	983	4	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	174962445	134	0	0
StatusRise_A	174962445	134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	134	0	0
T1	260543	0	0	0
T4	17308	0	0	0
T6	74903	0	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T26	983	3	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	3	0	0
T43	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174962445	134	0	0
T1	260543	0	0	0
T4	17308	0	0	0
T6	74903	0	0	0
T18	1233	0	0	0
T19	2413	0	0	0
T20	923	0	0	0
T26	983	3	0	0
T27	2069	0	0	0
T28	811	0	0	0
T29	1545	3	0	0
T43	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	6	0	0