Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	54316	0	0
CgEnOn_A	2147483647	44926	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	54316	0	0
T1	2939188	74	0	0
T4	1245758	45	0	0
T6	1270358	15	0	0
T7	14381	7	0	0
T8	13322	7	0	0
T9	18486	3	0	0
T18	53078	0	0	0
T19	11389	1	0	0
T20	19393	0	0	0
T24	26312	10	0	0
T25	24569	3	0	0
T26	82118	38	0	0
T27	28502	3	0	0
T28	20782	3	0	0
T29	16606	37	0	0
T42	0	6	0	0
T43	0	25	0	0
T152	0	15	0	0
T153	0	5	0	0
T154	0	25	0	0
T155	0	20	0	0
T156	0	30	0	0
T157	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44926	0	0
T1	2939188	445	0	0
T3	0	32	0	0
T4	1245758	0	0	0
T6	1834076	66	0	0
T7	9364	9	0	0
T8	13322	5	0	0
T9	18486	0	0	0
T18	53078	0	0	0
T19	11389	5	0	0
T20	19393	7	0	0
T22	0	44	0	0
T24	26312	17	0	0
T25	24569	0	0	0
T26	82118	41	0	0
T27	28502	0	0	0
T28	20782	0	0	0
T29	16606	38	0	0
T31	0	1	0	0
T42	0	8	0	0
T43	0	29	0	0
T134	0	34	0	0
T152	0	17	0	0
T153	0	6	0	0
T154	0	28	0	0
T155	0	24	0	0
T156	0	35	0	0
T157	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	305187244	150	0	0
CgEnOn_A	305187244	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187244	150	0	0
T1	298557	0	0	0
T4	36966	0	0	0
T6	118437	0	0	0
T18	5807	0	0	0
T19	1133	0	0	0
T20	1977	0	0	0
T26	4008	4	0	0
T27	1313	0	0	0
T28	905	0	0	0
T29	731	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187244	150	0	0
T1	298557	0	0	0
T4	36966	0	0	0
T6	118437	0	0	0
T18	5807	0	0	0
T19	1133	0	0	0
T20	1977	0	0	0
T26	4008	4	0	0
T27	1313	0	0	0
T28	905	0	0	0
T29	731	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	152592897	150	0	0
CgEnOn_A	152592897	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152592897	150	0	0
T1	149277	0	0	0
T4	18484	0	0	0
T6	59217	0	0	0
T18	2903	0	0	0
T19	567	0	0	0
T20	988	0	0	0
T26	2004	4	0	0
T27	655	0	0	0
T28	452	0	0	0
T29	366	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152592897	150	0	0
T1	149277	0	0	0
T4	18484	0	0	0
T6	59217	0	0	0
T18	2903	0	0	0
T19	567	0	0	0
T20	988	0	0	0
T26	2004	4	0	0
T27	655	0	0	0
T28	452	0	0	0
T29	366	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	152592897	150	0	0
CgEnOn_A	152592897	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152592897	150	0	0
T1	149277	0	0	0
T4	18484	0	0	0
T6	59217	0	0	0
T18	2903	0	0	0
T19	567	0	0	0
T20	988	0	0	0
T26	2004	4	0	0
T27	655	0	0	0
T28	452	0	0	0
T29	366	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152592897	150	0	0
T1	149277	0	0	0
T4	18484	0	0	0
T6	59217	0	0	0
T18	2903	0	0	0
T19	567	0	0	0
T20	988	0	0	0
T26	2004	4	0	0
T27	655	0	0	0
T28	452	0	0	0
T29	366	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	152592897	150	0	0
CgEnOn_A	152592897	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152592897	150	0	0
T1	149277	0	0	0
T4	18484	0	0	0
T6	59217	0	0	0
T18	2903	0	0	0
T19	567	0	0	0
T20	988	0	0	0
T26	2004	4	0	0
T27	655	0	0	0
T28	452	0	0	0
T29	366	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152592897	150	0	0
T1	149277	0	0	0
T4	18484	0	0	0
T6	59217	0	0	0
T18	2903	0	0	0
T19	567	0	0	0
T20	988	0	0	0
T26	2004	4	0	0
T27	655	0	0	0
T28	452	0	0	0
T29	366	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	611740057	150	0	0
CgEnOn_A	611740057	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740057	150	0	0
T1	597636	0	0	0
T4	118688	0	0	0
T6	236252	0	0	0
T18	10761	0	0	0
T19	2387	0	0	0
T20	4033	0	0	0
T26	8122	4	0	0
T27	2514	0	0	0
T28	1856	0	0	0
T29	1487	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740057	141	0	0
T1	597636	0	0	0
T4	118688	0	0	0
T6	236252	0	0	0
T18	10761	0	0	0
T19	2387	0	0	0
T20	4033	0	0	0
T26	8122	4	0	0
T27	2514	0	0	0
T28	1856	0	0	0
T29	1487	4	0	0
T42	0	1	0	0
T43	0	5	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	649318036	134	0	0
CgEnOn_A	649318036	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	134	0	0
T1	643558	0	0	0
T4	123637	0	0	0
T6	294103	0	0	0
T18	11210	0	0	0
T19	2487	0	0	0
T20	4201	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T31	0	1	0	0
T42	0	1	0	0
T43	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	132	0	0
T1	643558	0	0	0
T4	123637	0	0	0
T6	294103	0	0	0
T18	11210	0	0	0
T19	2487	0	0	0
T20	4201	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T31	0	1	0	0
T42	0	1	0	0
T43	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	649318036	134	0	0
CgEnOn_A	649318036	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	134	0	0
T1	643558	0	0	0
T4	123637	0	0	0
T6	294103	0	0	0
T18	11210	0	0	0
T19	2487	0	0	0
T20	4201	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T31	0	1	0	0
T42	0	1	0	0
T43	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	132	0	0
T1	643558	0	0	0
T4	123637	0	0	0
T6	294103	0	0	0
T18	11210	0	0	0
T19	2487	0	0	0
T20	4201	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T31	0	1	0	0
T42	0	1	0	0
T43	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	4	0	0
T156	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	311933295	137	0	0
CgEnOn_A	311933295	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311933295	137	0	0
T1	308048	0	0	0
T4	59346	0	0	0
T6	149812	0	0	0
T18	5381	0	0	0
T19	1194	0	0	0
T20	2017	0	0	0
T26	3633	3	0	0
T27	1257	0	0	0
T28	927	0	0	0
T29	733	3	0	0
T43	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311933295	134	0	0
T1	308048	0	0	0
T4	59346	0	0	0
T6	149812	0	0	0
T18	5381	0	0	0
T19	1194	0	0	0
T20	2017	0	0	0
T26	3633	3	0	0
T27	1257	0	0	0
T28	927	0	0	0
T29	733	3	0	0
T43	0	3	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T29,T42
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	152592897	8737	0	0
CgEnOn_A	152592897	6400	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152592897	8737	0	0
T4	18484	15	0	0
T7	549	1	0	0
T8	508	2	0	0
T9	715	1	0	0
T24	1005	1	0	0
T25	967	1	0	0
T26	2004	5	0	0
T27	655	1	0	0
T28	452	1	0	0
T29	366	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152592897	6400	0	0
T1	0	98	0	0
T3	0	4	0	0
T4	18484	0	0	0
T6	59217	13	0	0
T8	508	1	0	0
T9	715	0	0	0
T19	0	1	0	0
T20	0	2	0	0
T22	0	15	0	0
T24	1005	0	0	0
T25	967	0	0	0
T26	2004	4	0	0
T27	655	0	0	0
T28	452	0	0	0
T29	366	4	0	0
T134	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T29,T42
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	305187244	8750	0	0
CgEnOn_A	305187244	6413	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187244	8750	0	0
T4	36966	15	0	0
T7	1097	1	0	0
T8	1015	2	0	0
T9	1429	1	0	0
T24	2009	1	0	0
T25	1935	1	0	0
T26	4008	5	0	0
T27	1313	1	0	0
T28	905	1	0	0
T29	731	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	305187244	6413	0	0
T1	0	104	0	0
T3	0	5	0	0
T4	36966	0	0	0
T6	118437	12	0	0
T8	1015	1	0	0
T9	1429	0	0	0
T19	0	1	0	0
T20	0	2	0	0
T22	0	14	0	0
T24	2009	0	0	0
T25	1935	0	0	0
T26	4008	4	0	0
T27	1313	0	0	0
T28	905	0	0	0
T29	731	4	0	0
T134	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T29,T42
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	611740057	8753	0	0
CgEnOn_A	611740057	6407	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740057	8753	0	0
T4	118688	15	0	0
T7	2247	1	0	0
T8	2082	2	0	0
T9	2884	1	0	0
T24	4111	1	0	0
T25	3823	1	0	0
T26	8122	5	0	0
T27	2514	1	0	0
T28	1856	1	0	0
T29	1487	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611740057	6407	0	0
T1	0	101	0	0
T3	0	5	0	0
T4	118688	0	0	0
T6	236252	12	0	0
T8	2082	1	0	0
T9	2884	0	0	0
T19	0	1	0	0
T20	0	3	0	0
T22	0	15	0	0
T24	4111	0	0	0
T25	3823	0	0	0
T26	8122	4	0	0
T27	2514	0	0	0
T28	1856	0	0	0
T29	1487	4	0	0
T134	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T29,T43
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	311933295	8761	0	0
CgEnOn_A	311933295	6415	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311933295	8761	0	0
T4	59346	15	0	0
T7	1124	1	0	0
T8	1041	2	0	0
T9	1442	1	0	0
T24	2055	1	0	0
T25	1912	1	0	0
T26	3633	4	0	0
T27	1257	1	0	0
T28	927	1	0	0
T29	733	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	311933295	6415	0	0
T1	0	96	0	0
T3	0	5	0	0
T4	59346	0	0	0
T6	149812	11	0	0
T8	1041	1	0	0
T9	1442	0	0	0
T19	0	1	0	0
T20	0	3	0	0
T22	0	14	0	0
T24	2055	0	0	0
T25	1912	0	0	0
T26	3633	3	0	0
T27	1257	0	0	0
T28	927	0	0	0
T29	733	3	0	0
T134	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Covered	T7,T8,T24
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	649318036	4570	0	0
CgEnOn_A	649318036	4568	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	4570	0	0
T1	0	74	0	0
T3	0	8	0	0
T4	123637	0	0	0
T6	0	15	0	0
T7	2341	4	0	0
T8	2169	1	0	0
T9	3004	0	0	0
T19	0	1	0	0
T24	4283	7	0	0
T25	3983	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T42	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	4568	0	0
T1	0	74	0	0
T3	0	8	0	0
T4	123637	0	0	0
T6	0	15	0	0
T7	2341	4	0	0
T8	2169	1	0	0
T9	3004	0	0	0
T19	0	1	0	0
T24	4283	7	0	0
T25	3983	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T42	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Covered	T7,T8,T24
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	649318036	4540	0	0
CgEnOn_A	649318036	4538	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	4540	0	0
T1	0	68	0	0
T3	0	10	0	0
T4	123637	0	0	0
T6	0	14	0	0
T7	2341	5	0	0
T8	2169	1	0	0
T9	3004	0	0	0
T19	0	1	0	0
T24	4283	10	0	0
T25	3983	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T42	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	4538	0	0
T1	0	68	0	0
T3	0	10	0	0
T4	123637	0	0	0
T6	0	14	0	0
T7	2341	5	0	0
T8	2169	1	0	0
T9	3004	0	0	0
T19	0	1	0	0
T24	4283	10	0	0
T25	3983	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T42	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Covered	T7,T8,T24
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	649318036	4532	0	0
CgEnOn_A	649318036	4530	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	4532	0	0
T1	0	69	0	0
T3	0	10	0	0
T4	123637	0	0	0
T6	0	21	0	0
T7	2341	7	0	0
T8	2169	1	0	0
T9	3004	0	0	0
T19	0	1	0	0
T24	4283	7	0	0
T25	3983	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T42	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	4530	0	0
T1	0	69	0	0
T3	0	10	0	0
T4	123637	0	0	0
T6	0	21	0	0
T7	2341	7	0	0
T8	2169	1	0	0
T9	3004	0	0	0
T19	0	1	0	0
T24	4283	7	0	0
T25	3983	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T42	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T26,T4,T29
1	0	Covered	T7,T8,T24
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	649318036	4518	0	0
CgEnOn_A	649318036	4516	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	4518	0	0
T1	0	78	0	0
T3	0	7	0	0
T4	123637	0	0	0
T6	0	19	0	0
T7	2341	3	0	0
T8	2169	1	0	0
T9	3004	0	0	0
T19	0	1	0	0
T24	4283	13	0	0
T25	3983	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T42	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649318036	4516	0	0
T1	0	78	0	0
T3	0	7	0	0
T4	123637	0	0	0
T6	0	19	0	0
T7	2341	3	0	0
T8	2169	1	0	0
T9	3004	0	0	0
T19	0	1	0	0
T24	4283	13	0	0
T25	3983	0	0	0
T26	7096	3	0	0
T27	2619	0	0	0
T28	1933	0	0	0
T29	1540	2	0	0
T42	0	1	0	0