Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	824022991	14951	0	0
GateOpen_A	824022991	21391	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824022991	14951	0	0
T1	1723121	235	0	0
T2	1452570	252	0	0
T3	1812988	79	0	0
T5	10934	4	0	0
T11	0	14	0	0
T14	0	75	0	0
T16	4368	0	0	0
T17	4724	0	0	0
T18	5827	0	0	0
T19	5382	0	0	0
T20	67764	0	0	0
T21	187698	0	0	0
T22	0	13	0	0
T33	0	6	0	0
T66	0	21	0	0
T117	0	4	0	0
T148	0	25	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824022991	21391	0	0
T1	1723121	239	0	0
T2	1452570	276	0	0
T3	1812988	95	0	0
T4	11487	4	0	0
T5	10934	8	0	0
T16	4368	0	0	0
T17	4724	4	0	0
T18	5827	0	0	0
T19	5382	4	0	0
T20	67764	16	0	0
T21	0	72	0	0
T60	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	90705923	3523	0	0
GateOpen_A	90705923	5131	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705923	3523	0	0
T1	953038	57	0	0
T2	799302	59	0	0
T3	198566	18	0	0
T5	1204	1	0	0
T11	0	3	0	0
T16	470	0	0	0
T17	505	0	0	0
T18	632	0	0	0
T19	578	0	0	0
T20	5430	0	0	0
T21	14042	0	0	0
T22	0	3	0	0
T33	0	2	0	0
T66	0	4	0	0
T117	0	1	0	0
T148	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705923	5131	0	0
T1	953038	58	0	0
T2	799302	65	0	0
T3	198566	22	0	0
T4	1323	1	0	0
T5	1204	2	0	0
T16	470	0	0	0
T17	505	1	0	0
T18	632	0	0	0
T19	578	1	0	0
T20	5430	4	0	0
T21	0	18	0	0
T60	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	181412665	3798	0	0
GateOpen_A	181412665	5406	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181412665	3798	0	0
T1	190611	59	0	0
T2	159861	64	0	0
T3	397136	22	0	0
T5	2408	1	0	0
T11	0	3	0	0
T16	940	0	0	0
T17	1010	0	0	0
T18	1264	0	0	0
T19	1156	0	0	0
T20	10859	0	0	0
T21	28085	0	0	0
T22	0	4	0	0
T33	0	2	0	0
T66	0	6	0	0
T117	0	1	0	0
T148	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181412665	5406	0	0
T1	190611	60	0	0
T2	159861	70	0	0
T3	397136	26	0	0
T4	2647	1	0	0
T5	2408	2	0	0
T16	940	0	0	0
T17	1010	1	0	0
T18	1264	0	0	0
T19	1156	1	0	0
T20	10859	4	0	0
T21	0	18	0	0
T60	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	364627964	3811	0	0
GateOpen_A	364627964	5423	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364627964	3811	0	0
T1	381519	60	0	0
T2	321061	62	0	0
T3	794231	21	0	0
T5	4881	1	0	0
T11	0	4	0	0
T16	1972	0	0	0
T17	2139	0	0	0
T18	2621	0	0	0
T19	2432	0	0	0
T20	34316	0	0	0
T21	97046	0	0	0
T22	0	3	0	0
T33	0	2	0	0
T66	0	6	0	0
T117	0	1	0	0
T148	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364627964	5423	0	0
T1	381519	61	0	0
T2	321061	68	0	0
T3	794231	25	0	0
T4	5011	1	0	0
T5	4881	2	0	0
T16	1972	0	0	0
T17	2139	1	0	0
T18	2621	0	0	0
T19	2432	1	0	0
T20	34316	4	0	0
T21	0	18	0	0
T60	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T34,T35,T36
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	187276439	3819	0	0
GateOpen_A	187276439	5431	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187276439	3819	0	0
T1	197953	59	0	0
T2	172346	67	0	0
T3	423055	18	0	0
T5	2441	1	0	0
T11	0	4	0	0
T14	0	75	0	0
T16	986	0	0	0
T17	1070	0	0	0
T18	1310	0	0	0
T19	1216	0	0	0
T20	17159	0	0	0
T21	48525	0	0	0
T22	0	3	0	0
T66	0	5	0	0
T117	0	1	0	0
T148	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187276439	5431	0	0
T1	197953	60	0	0
T2	172346	73	0	0
T3	423055	22	0	0
T4	2506	1	0	0
T5	2441	2	0	0
T16	986	0	0	0
T17	1070	1	0	0
T18	1310	0	0	0
T19	1216	1	0	0
T20	17159	4	0	0
T21	0	18	0	0
T60	0	1	0	0