Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	807973815	75756	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807973815	75756	0	0
T1	1573520	502	0	0
T2	1757940	2296	0	0
T3	2115275	710	0	0
T5	6350	0	0	0
T9	0	204	0	0
T10	0	157	0	0
T11	0	489	0	0
T12	0	242	0	0
T13	0	113	0	0
T14	0	2102	0	0
T15	0	332	0	0
T16	10065	0	0	0
T17	5460	0	0	0
T18	3405	0	0	0
T19	12155	0	0	0
T20	42890	0	0	0
T21	353810	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161594763	10855	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	10855	0	0
T1	314704	67	0	0
T2	351588	338	0	0
T3	423055	103	0	0
T5	1270	0	0	0
T9	0	30	0	0
T10	0	25	0	0
T11	0	64	0	0
T12	0	39	0	0
T13	0	17	0	0
T14	0	307	0	0
T15	0	53	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T21	70762	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161594763	10681	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	10681	0	0
T1	314704	65	0	0
T2	351588	285	0	0
T3	423055	103	0	0
T5	1270	0	0	0
T9	0	26	0	0
T10	0	25	0	0
T11	0	63	0	0
T12	0	39	0	0
T13	0	17	0	0
T14	0	304	0	0
T15	0	53	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T21	70762	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161594763	15252	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	15252	0	0
T1	314704	103	0	0
T2	351588	451	0	0
T3	423055	158	0	0
T5	1270	0	0	0
T9	0	40	0	0
T10	0	32	0	0
T11	0	100	0	0
T12	0	49	0	0
T13	0	23	0	0
T14	0	420	0	0
T15	0	67	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T21	70762	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161594763	15263	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	15263	0	0
T1	314704	99	0	0
T2	351588	465	0	0
T3	423055	138	0	0
T5	1270	0	0	0
T9	0	42	0	0
T10	0	32	0	0
T11	0	99	0	0
T12	0	49	0	0
T13	0	22	0	0
T14	0	422	0	0
T15	0	67	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T21	70762	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161594763	23705	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	23705	0	0
T1	314704	168	0	0
T2	351588	757	0	0
T3	423055	208	0	0
T5	1270	0	0	0
T9	0	66	0	0
T10	0	43	0	0
T11	0	163	0	0
T12	0	66	0	0
T13	0	34	0	0
T14	0	649	0	0
T15	0	92	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T21	70762	0	0	0