Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	161594763	158790660	0	0
AllClkBypReqTrue_A	161594763	132591	0	0
IoClkBypReqFalse_A	161594763	158710974	0	2415
IoClkBypReqTrue_A	161594763	207661	0	0
LcClkBypAckFalse_A	161594763	158801056	0	0
LcClkBypAckTrue_A	161594763	122195	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	158790660	0	0
T1	314704	312503	0	0
T2	351588	347615	0	0
T3	423055	421817	0	0
T4	1252	1156	0	0
T5	1270	1224	0	0
T16	2013	1819	0	0
T17	1092	1015	0	0
T18	681	624	0	0
T19	2431	2200	0	0
T20	8578	2407	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	132591	0	0
T1	314704	2491	0	0
T2	351588	1923	0	0
T3	423055	424	0	0
T4	1252	51	0	0
T5	1270	0	0	0
T11	0	173	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T68	0	59	0	0
T70	0	36	0	0
T111	0	37	0	0
T112	0	13	0	0
T113	0	96	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	158710974	0	2415
T1	314704	312311	0	3
T2	351588	347478	0	3
T3	423055	421667	0	3
T4	1252	1107	0	3
T5	1270	1222	0	3
T16	2013	1817	0	3
T17	1092	1013	0	3
T18	681	622	0	3
T19	2431	2198	0	3
T20	8578	2397	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	207661	0	0
T1	314704	4394	0	0
T2	351588	3269	0	0
T3	423055	556	0	0
T4	1252	98	0	0
T5	1270	0	0	0
T11	0	435	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T68	0	27	0	0
T69	0	678	0	0
T70	0	324	0	0
T111	0	236	0	0
T113	0	186	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	158801056	0	0
T1	314704	312508	0	0
T2	351588	347623	0	0
T3	423055	421888	0	0
T4	1252	1155	0	0
T5	1270	1224	0	0
T16	2013	1819	0	0
T17	1092	1015	0	0
T18	681	624	0	0
T19	2431	2200	0	0
T20	8578	2407	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	122195	0	0
T1	314704	2445	0	0
T2	351588	1842	0	0
T3	423055	353	0	0
T4	1252	52	0	0
T5	1270	0	0	0
T11	0	152	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T69	0	267	0	0
T70	0	181	0	0
T111	0	165	0	0
T113	0	134	0	0
T114	0	140	0	0