Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1561008800	16297	0	0
TransStop_A	1561008800	8340	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1561008800	16297	0	0
T1	1668780	284	0	0
T2	1445796	233	0	0
T3	3453400	76	0	0
T5	20340	4	0	0
T16	8216	14	0	0
T17	8916	0	0	0
T18	10920	0	0	0
T19	10136	12	0	0
T20	142988	0	0	0
T21	404368	0	0	0
T22	0	10	0	0
T60	0	3	0	0
T65	0	34	0	0
T115	0	5	0	0
T116	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1561008800	8340	0	0
T1	1668780	141	0	0
T2	1445796	116	0	0
T3	3453400	39	0	0
T5	20340	4	0	0
T11	0	1	0	0
T14	0	46	0	0
T16	8216	11	0	0
T17	8916	0	0	0
T18	10920	0	0	0
T19	10136	7	0	0
T20	142988	0	0	0
T21	404368	0	0	0
T22	0	2	0	0
T65	0	16	0	0
T115	0	5	0	0
T117	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	390252200	4047	0	0
TransStop_A	390252200	2048	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390252200	4047	0	0
T1	417195	74	0	0
T2	361449	55	0	0
T3	863350	23	0	0
T5	5085	1	0	0
T16	2054	5	0	0
T17	2229	0	0	0
T18	2730	0	0	0
T19	2534	3	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	1	0	0
T60	0	1	0	0
T65	0	6	0	0
T115	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390252200	2048	0	0
T1	417195	39	0	0
T2	361449	24	0	0
T3	863350	11	0	0
T5	5085	1	0	0
T11	0	1	0	0
T16	2054	4	0	0
T17	2229	0	0	0
T18	2730	0	0	0
T19	2534	1	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T65	0	3	0	0
T115	0	2	0	0
T117	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	390252200	4104	0	0
TransStop_A	390252200	2135	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390252200	4104	0	0
T1	417195	75	0	0
T2	361449	57	0	0
T3	863350	15	0	0
T5	5085	1	0	0
T16	2054	4	0	0
T17	2229	0	0	0
T18	2730	0	0	0
T19	2534	3	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	4	0	0
T60	0	1	0	0
T65	0	11	0	0
T115	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390252200	2135	0	0
T1	417195	38	0	0
T2	361449	30	0	0
T3	863350	7	0	0
T5	5085	1	0	0
T16	2054	3	0	0
T17	2229	0	0	0
T18	2730	0	0	0
T19	2534	1	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	1	0	0
T65	0	7	0	0
T115	0	1	0	0
T117	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	390252200	4109	0	0
TransStop_A	390252200	2093	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390252200	4109	0	0
T1	417195	65	0	0
T2	361449	63	0	0
T3	863350	19	0	0
T5	5085	1	0	0
T16	2054	1	0	0
T17	2229	0	0	0
T18	2730	0	0	0
T19	2534	2	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	2	0	0
T65	0	6	0	0
T115	0	1	0	0
T116	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390252200	2093	0	0
T1	417195	30	0	0
T2	361449	31	0	0
T3	863350	10	0	0
T5	5085	1	0	0
T14	0	46	0	0
T16	2054	1	0	0
T17	2229	0	0	0
T18	2730	0	0	0
T19	2534	2	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T65	0	1	0	0
T115	0	1	0	0
T117	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	390252200	4037	0	0
TransStop_A	390252200	2064	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390252200	4037	0	0
T1	417195	70	0	0
T2	361449	58	0	0
T3	863350	19	0	0
T5	5085	1	0	0
T16	2054	4	0	0
T17	2229	0	0	0
T18	2730	0	0	0
T19	2534	4	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	3	0	0
T60	0	1	0	0
T65	0	11	0	0
T115	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390252200	2064	0	0
T1	417195	34	0	0
T2	361449	31	0	0
T3	863350	11	0	0
T5	5085	1	0	0
T16	2054	3	0	0
T17	2229	0	0	0
T18	2730	0	0	0
T19	2534	3	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	1	0	0
T65	0	5	0	0
T115	0	1	0	0
T117	0	1	0	0