Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10CoveredT4,T1,T2 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT4,T1,T2
11CoveredT4,T1,T2 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT4,T1,T2
10CoveredT4,T1,T5
11CoveredT4,T1,T5
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 453285068 453282653 0 0
selKnown1 1093882626 1093880211 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 453285068 453282653 0 0
T1 1334070 1334068 0 0
T2 1118913 1118911 0 0
T3 992403 992400 0 0
T4 6456 6453 0 0
T5 6020 6017 0 0
T16 2348 2345 0 0
T17 2523 2520 0 0
T18 3158 3155 0 0
T19 2888 2885 0 0
T20 27145 27142 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1093882626 1093880211 0 0
T1 1144557 1144557 0 0
T2 963183 963183 0 0
T3 2382693 2382690 0 0
T4 15030 15027 0 0
T5 14643 14640 0 0
T16 5913 5910 0 0
T17 6417 6414 0 0
T18 7860 7857 0 0
T19 7293 7290 0 0
T20 102948 102945 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T1,T5
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT4,T1,T5
11CoveredT4,T1,T5
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 181412249 181411444 0 0
selKnown1 364627542 364626737 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 181412249 181411444 0 0
T1 190611 190610 0 0
T2 159861 159861 0 0
T3 397135 397134 0 0
T4 2647 2646 0 0
T5 2408 2407 0 0
T16 939 938 0 0
T17 1009 1008 0 0
T18 1263 1262 0 0
T19 1155 1154 0 0
T20 10858 10857 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 364627542 364626737 0 0
T1 381519 381519 0 0
T2 321061 321061 0 0
T3 794231 794230 0 0
T4 5010 5009 0 0
T5 4881 4880 0 0
T16 1971 1970 0 0
T17 2139 2138 0 0
T18 2620 2619 0 0
T19 2431 2430 0 0
T20 34316 34315 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10CoveredT4,T1,T2 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T1,T5
10CoveredT4,T1,T2
11CoveredT4,T1,T2 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT4,T1,T2
10CoveredT4,T1,T5
11CoveredT4,T1,T5
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 181167290 181166485 0 0
selKnown1 364627542 364626737 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 181167290 181166485 0 0
T1 190421 190421 0 0
T2 159750 159749 0 0
T3 396703 396702 0 0
T4 2486 2485 0 0
T5 2408 2407 0 0
T16 939 938 0 0
T17 1009 1008 0 0
T18 1263 1262 0 0
T19 1155 1154 0 0
T20 10858 10857 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 364627542 364626737 0 0
T1 381519 381519 0 0
T2 321061 321061 0 0
T3 794231 794230 0 0
T4 5010 5009 0 0
T5 4881 4880 0 0
T16 1971 1970 0 0
T17 2139 2138 0 0
T18 2620 2619 0 0
T19 2431 2430 0 0
T20 34316 34315 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T1,T5
01CoveredT4,T1,T5
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T1,T5
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT4,T1,T5
11CoveredT4,T1,T5
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 90705529 90704724 0 0
selKnown1 364627542 364626737 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 90705529 90704724 0 0
T1 953038 953037 0 0
T2 799302 799301 0 0
T3 198565 198564 0 0
T4 1323 1322 0 0
T5 1204 1203 0 0
T16 470 469 0 0
T17 505 504 0 0
T18 632 631 0 0
T19 578 577 0 0
T20 5429 5428 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 364627542 364626737 0 0
T1 381519 381519 0 0
T2 321061 321061 0 0
T3 794231 794230 0 0
T4 5010 5009 0 0
T5 4881 4880 0 0
T16 1971 1970 0 0
T17 2139 2138 0 0
T18 2620 2619 0 0
T19 2431 2430 0 0
T20 34316 34315 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%