Module Definition
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Module : prim_lc_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_clkmgr_byp.u_en_sync 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_en_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1610 1610 0 0
OutputsKnown_A 323189526 317851118 0 0
gen_flops.OutputDelay_A 323189526 317836826 0 4830


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1610 1610 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 323189526 317851118 0 0
T1 629408 625506 0 0
T2 703176 695618 0 0
T3 846110 844500 0 0
T4 2504 2416 0 0
T5 2540 2450 0 0
T16 4026 3640 0 0
T17 2184 2032 0 0
T18 1362 1250 0 0
T19 4862 4402 0 0
T20 17156 4824 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 323189526 317836826 0 4830
T1 629408 625500 0 6
T2 703176 695610 0 6
T3 846110 844446 0 6
T4 2504 2410 0 6
T5 2540 2444 0 6
T16 4026 3634 0 6
T17 2184 2026 0 6
T18 1362 1244 0 6
T19 4862 4396 0 6
T20 17156 4794 0 6

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161594763 158925559 0 0
gen_flops.OutputDelay_A 161594763 158918413 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161594763 158925559 0 0
T1 314704 312753 0 0
T2 351588 347809 0 0
T3 423055 422250 0 0
T4 1252 1208 0 0
T5 1270 1225 0 0
T16 2013 1820 0 0
T17 1092 1016 0 0
T18 681 625 0 0
T19 2431 2201 0 0
T20 8578 2412 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161594763 158918413 0 2415
T1 314704 312750 0 3
T2 351588 347805 0 3
T3 423055 422223 0 3
T4 1252 1205 0 3
T5 1270 1222 0 3
T16 2013 1817 0 3
T17 1092 1013 0 3
T18 681 622 0 3
T19 2431 2198 0 3
T20 8578 2397 0 3

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 805 805 0 0
OutputsKnown_A 161594763 158925559 0 0
gen_flops.OutputDelay_A 161594763 158918413 0 2415


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161594763 158925559 0 0
T1 314704 312753 0 0
T2 351588 347809 0 0
T3 423055 422250 0 0
T4 1252 1208 0 0
T5 1270 1225 0 0
T16 2013 1820 0 0
T17 1092 1016 0 0
T18 681 625 0 0
T19 2431 2201 0 0
T20 8578 2412 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161594763 158918413 0 2415
T1 314704 312750 0 3
T2 351588 347805 0 3
T3 423055 422223 0 3
T4 1252 1205 0 3
T5 1270 1222 0 3
T16 2013 1817 0 3
T17 1092 1013 0 3
T18 681 622 0 3
T19 2431 2198 0 3
T20 8578 2397 0 3

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