Module Definition
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Module : clkmgr_lost_calib_regwen_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RegwenOff_A 161594763 20412797 0 56


RegwenOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 161594763 20412797 0 56
T1 314704 56360 0 0
T2 351588 262542 0 0
T3 423055 61085 0 1
T5 1270 0 0 0
T9 0 24113 0 1
T10 0 10029 0 1
T11 0 60012 0 0
T12 0 15075 0 1
T13 0 11005 0 1
T14 0 192067 0 0
T16 2013 0 0 0
T17 1092 0 0 0
T18 681 0 0 0
T19 2431 0 0 0
T20 8578 0 0 0
T21 70762 0 0 0
T22 0 821 0 0
T46 0 0 0 1
T73 0 0 0 1
T118 0 0 0 1
T119 0 0 0 1
T120 0 0 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%