Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	162560083	5428934	0	0
clk_enables_rd_A	162560083	42398	0	0
clk_hints_rd_A	162560083	36576	0	0
extclk_ctrl_rd_A	162560083	46885	0	0
extclk_ctrl_regwen_rd_A	162560083	35716	0	0
jitter_enable_rd_A	162560083	50401	0	0
jitter_regwen_rd_A	162560083	39641	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162560083	5428934	0	0
T1	314704	151993	0	0
T2	351588	120626	0	0
T3	423055	0	0	0
T5	1270	0	0	0
T14	0	179131	0	0
T16	2013	0	0	0
T17	1092	0	0	0
T18	681	0	0	0
T19	2431	0	0	0
T20	8578	0	0	0
T21	70762	0	0	0
T23	0	105178	0	0
T24	0	134608	0	0
T25	0	101767	0	0
T61	0	245986	0	0
T62	0	119884	0	0
T63	0	68051	0	0
T64	0	78168	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162560083	42398	0	0
T9	122538	0	0	0
T10	59771	0	0	0
T22	17118	6	0	0
T24	0	5293	0	0
T26	99444	0	0	0
T33	733	0	0	0
T111	1995	0	0	0
T112	804	0	0	0
T113	1492	0	0	0
T116	1624	0	0	0
T140	0	7	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	3479	0	0
T144	0	2	0	0
T145	0	3450	0	0
T146	0	9	0	0
T147	0	4695	0	0
T148	1826	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162560083	36576	0	0
T11	328052	0	0	0
T12	48332	0	0	0
T24	0	4567	0	0
T27	16318	0	0	0
T66	1064	0	0	0
T67	865	0	0	0
T68	1542	0	0	0
T69	2721	0	0	0
T70	1808	0	0	0
T71	26785	0	0	0
T117	2391	1	0	0
T140	0	7	0	0
T141	0	1	0	0
T142	0	7	0	0
T143	0	2904	0	0
T144	0	2	0	0
T145	0	2931	0	0
T146	0	8	0	0
T147	0	4172	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162560083	46885	0	0
T20	8578	14	0	0
T21	70762	0	0	0
T22	17118	0	0	0
T24	0	5971	0	0
T26	99444	107	0	0
T28	1154	0	0	0
T33	733	0	0	0
T60	1118	0	0	0
T65	2880	0	0	0
T69	0	64	0	0
T83	0	17	0	0
T114	0	43	0	0
T115	1354	0	0	0
T121	0	10	0	0
T148	1826	0	0	0
T149	0	2	0	0
T150	0	63	0	0
T151	0	18	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162560083	35716	0	0
T20	8578	12	0	0
T21	70762	0	0	0
T22	17118	0	0	0
T24	0	4646	0	0
T26	99444	51	0	0
T28	1154	0	0	0
T33	733	0	0	0
T60	1118	0	0	0
T65	2880	0	0	0
T75	0	40	0	0
T110	0	32	0	0
T115	1354	0	0	0
T143	0	2745	0	0
T145	0	2858	0	0
T147	0	4387	0	0
T148	1826	0	0	0
T152	0	29	0	0
T153	0	30	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162560083	50401	0	0
T9	122538	0	0	0
T10	59771	0	0	0
T22	17118	111	0	0
T24	0	6165	0	0
T26	99444	0	0	0
T33	733	0	0	0
T111	1995	0	0	0
T112	804	0	0	0
T113	1492	0	0	0
T116	1624	0	0	0
T117	0	126	0	0
T140	0	95	0	0
T141	0	101	0	0
T142	0	111	0	0
T143	0	3538	0	0
T144	0	120	0	0
T148	1826	0	0	0
T154	0	52	0	0
T155	0	91	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162560083	39641	0	0
T24	473613	5173	0	0
T25	209539	0	0	0
T34	926	0	0	0
T74	137080	0	0	0
T140	760953	0	0	0
T143	0	3182	0	0
T145	0	3207	0	0
T147	0	4974	0	0
T151	1796	0	0	0
T156	0	5241	0	0
T157	0	1838	0	0
T158	0	2933	0	0
T159	0	1761	0	0
T160	0	3211	0	0
T161	0	2897	0	0
T162	586	0	0	0
T163	2158	0	0	0
T164	2901	0	0	0
T165	942	0	0	0