SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T1,T16 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 364627964 | 4313 | 0 | 0 |
g_div2.Div2Whole_A | 364627964 | 5107 | 0 | 0 |
g_div4.Div4Stepped_A | 181412665 | 4220 | 0 | 0 |
g_div4.Div4Whole_A | 181412665 | 4862 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 364627964 | 4313 | 0 | 0 |
T1 | 381519 | 94 | 0 | 0 |
T2 | 321061 | 49 | 0 | 0 |
T3 | 794231 | 17 | 0 | 0 |
T4 | 5011 | 3 | 0 | 0 |
T5 | 4881 | 0 | 0 | 0 |
T11 | 0 | 6 | 0 | 0 |
T16 | 1972 | 0 | 0 | 0 |
T17 | 2139 | 0 | 0 | 0 |
T18 | 2621 | 0 | 0 | 0 |
T19 | 2432 | 0 | 0 | 0 |
T20 | 34316 | 0 | 0 | 0 |
T68 | 0 | 9 | 0 | 0 |
T69 | 0 | 6 | 0 | 0 |
T111 | 0 | 5 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 364627964 | 5107 | 0 | 0 |
T1 | 381519 | 122 | 0 | 0 |
T2 | 321061 | 69 | 0 | 0 |
T3 | 794231 | 22 | 0 | 0 |
T4 | 5011 | 4 | 0 | 0 |
T5 | 4881 | 0 | 0 | 0 |
T11 | 0 | 8 | 0 | 0 |
T16 | 1972 | 0 | 0 | 0 |
T17 | 2139 | 0 | 0 | 0 |
T18 | 2621 | 0 | 0 | 0 |
T19 | 2432 | 0 | 0 | 0 |
T20 | 34316 | 0 | 0 | 0 |
T68 | 0 | 9 | 0 | 0 |
T69 | 0 | 12 | 0 | 0 |
T111 | 0 | 9 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 181412665 | 4220 | 0 | 0 |
T1 | 190611 | 93 | 0 | 0 |
T2 | 159861 | 48 | 0 | 0 |
T3 | 397136 | 17 | 0 | 0 |
T4 | 2647 | 3 | 0 | 0 |
T5 | 2408 | 0 | 0 | 0 |
T11 | 0 | 5 | 0 | 0 |
T16 | 940 | 0 | 0 | 0 |
T17 | 1010 | 0 | 0 | 0 |
T18 | 1264 | 0 | 0 | 0 |
T19 | 1156 | 0 | 0 | 0 |
T20 | 10859 | 0 | 0 | 0 |
T68 | 0 | 9 | 0 | 0 |
T69 | 0 | 6 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 181412665 | 4862 | 0 | 0 |
T1 | 190611 | 116 | 0 | 0 |
T2 | 159861 | 64 | 0 | 0 |
T3 | 397136 | 22 | 0 | 0 |
T4 | 2647 | 4 | 0 | 0 |
T5 | 2408 | 0 | 0 | 0 |
T11 | 0 | 6 | 0 | 0 |
T16 | 940 | 0 | 0 | 0 |
T17 | 1010 | 0 | 0 | 0 |
T18 | 1264 | 0 | 0 | 0 |
T19 | 1156 | 0 | 0 | 0 |
T20 | 10859 | 0 | 0 | 0 |
T68 | 0 | 8 | 0 | 0 |
T69 | 0 | 12 | 0 | 0 |
T111 | 0 | 6 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 6 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T1,T16 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 364627964 | 4313 | 0 | 0 |
g_div2.Div2Whole_A | 364627964 | 5107 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 364627964 | 4313 | 0 | 0 |
T1 | 381519 | 94 | 0 | 0 |
T2 | 321061 | 49 | 0 | 0 |
T3 | 794231 | 17 | 0 | 0 |
T4 | 5011 | 3 | 0 | 0 |
T5 | 4881 | 0 | 0 | 0 |
T11 | 0 | 6 | 0 | 0 |
T16 | 1972 | 0 | 0 | 0 |
T17 | 2139 | 0 | 0 | 0 |
T18 | 2621 | 0 | 0 | 0 |
T19 | 2432 | 0 | 0 | 0 |
T20 | 34316 | 0 | 0 | 0 |
T68 | 0 | 9 | 0 | 0 |
T69 | 0 | 6 | 0 | 0 |
T111 | 0 | 5 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 364627964 | 5107 | 0 | 0 |
T1 | 381519 | 122 | 0 | 0 |
T2 | 321061 | 69 | 0 | 0 |
T3 | 794231 | 22 | 0 | 0 |
T4 | 5011 | 4 | 0 | 0 |
T5 | 4881 | 0 | 0 | 0 |
T11 | 0 | 8 | 0 | 0 |
T16 | 1972 | 0 | 0 | 0 |
T17 | 2139 | 0 | 0 | 0 |
T18 | 2621 | 0 | 0 | 0 |
T19 | 2432 | 0 | 0 | 0 |
T20 | 34316 | 0 | 0 | 0 |
T68 | 0 | 9 | 0 | 0 |
T69 | 0 | 12 | 0 | 0 |
T111 | 0 | 9 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 6 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T1,T16 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T4,T1,T2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 181412665 | 4220 | 0 | 0 |
g_div4.Div4Whole_A | 181412665 | 4862 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 181412665 | 4220 | 0 | 0 |
T1 | 190611 | 93 | 0 | 0 |
T2 | 159861 | 48 | 0 | 0 |
T3 | 397136 | 17 | 0 | 0 |
T4 | 2647 | 3 | 0 | 0 |
T5 | 2408 | 0 | 0 | 0 |
T11 | 0 | 5 | 0 | 0 |
T16 | 940 | 0 | 0 | 0 |
T17 | 1010 | 0 | 0 | 0 |
T18 | 1264 | 0 | 0 | 0 |
T19 | 1156 | 0 | 0 | 0 |
T20 | 10859 | 0 | 0 | 0 |
T68 | 0 | 9 | 0 | 0 |
T69 | 0 | 6 | 0 | 0 |
T111 | 0 | 4 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 5 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 181412665 | 4862 | 0 | 0 |
T1 | 190611 | 116 | 0 | 0 |
T2 | 159861 | 64 | 0 | 0 |
T3 | 397136 | 22 | 0 | 0 |
T4 | 2647 | 4 | 0 | 0 |
T5 | 2408 | 0 | 0 | 0 |
T11 | 0 | 6 | 0 | 0 |
T16 | 940 | 0 | 0 | 0 |
T17 | 1010 | 0 | 0 | 0 |
T18 | 1264 | 0 | 0 | 0 |
T19 | 1156 | 0 | 0 | 0 |
T20 | 10859 | 0 | 0 | 0 |
T68 | 0 | 8 | 0 | 0 |
T69 | 0 | 12 | 0 | 0 |
T111 | 0 | 6 | 0 | 0 |
T112 | 0 | 1 | 0 | 0 |
T113 | 0 | 6 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |