Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T1,T16
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 364627964 4313 0 0
g_div2.Div2Whole_A 364627964 5107 0 0
g_div4.Div4Stepped_A 181412665 4220 0 0
g_div4.Div4Whole_A 181412665 4862 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 364627964 4313 0 0
T1 381519 94 0 0
T2 321061 49 0 0
T3 794231 17 0 0
T4 5011 3 0 0
T5 4881 0 0 0
T11 0 6 0 0
T16 1972 0 0 0
T17 2139 0 0 0
T18 2621 0 0 0
T19 2432 0 0 0
T20 34316 0 0 0
T68 0 9 0 0
T69 0 6 0 0
T111 0 5 0 0
T112 0 1 0 0
T113 0 5 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 364627964 5107 0 0
T1 381519 122 0 0
T2 321061 69 0 0
T3 794231 22 0 0
T4 5011 4 0 0
T5 4881 0 0 0
T11 0 8 0 0
T16 1972 0 0 0
T17 2139 0 0 0
T18 2621 0 0 0
T19 2432 0 0 0
T20 34316 0 0 0
T68 0 9 0 0
T69 0 12 0 0
T111 0 9 0 0
T112 0 1 0 0
T113 0 6 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181412665 4220 0 0
T1 190611 93 0 0
T2 159861 48 0 0
T3 397136 17 0 0
T4 2647 3 0 0
T5 2408 0 0 0
T11 0 5 0 0
T16 940 0 0 0
T17 1010 0 0 0
T18 1264 0 0 0
T19 1156 0 0 0
T20 10859 0 0 0
T68 0 9 0 0
T69 0 6 0 0
T111 0 4 0 0
T112 0 1 0 0
T113 0 5 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181412665 4862 0 0
T1 190611 116 0 0
T2 159861 64 0 0
T3 397136 22 0 0
T4 2647 4 0 0
T5 2408 0 0 0
T11 0 6 0 0
T16 940 0 0 0
T17 1010 0 0 0
T18 1264 0 0 0
T19 1156 0 0 0
T20 10859 0 0 0
T68 0 8 0 0
T69 0 12 0 0
T111 0 6 0 0
T112 0 1 0 0
T113 0 6 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T1,T16
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 364627964 4313 0 0
g_div2.Div2Whole_A 364627964 5107 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 364627964 4313 0 0
T1 381519 94 0 0
T2 321061 49 0 0
T3 794231 17 0 0
T4 5011 3 0 0
T5 4881 0 0 0
T11 0 6 0 0
T16 1972 0 0 0
T17 2139 0 0 0
T18 2621 0 0 0
T19 2432 0 0 0
T20 34316 0 0 0
T68 0 9 0 0
T69 0 6 0 0
T111 0 5 0 0
T112 0 1 0 0
T113 0 5 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 364627964 5107 0 0
T1 381519 122 0 0
T2 321061 69 0 0
T3 794231 22 0 0
T4 5011 4 0 0
T5 4881 0 0 0
T11 0 8 0 0
T16 1972 0 0 0
T17 2139 0 0 0
T18 2621 0 0 0
T19 2432 0 0 0
T20 34316 0 0 0
T68 0 9 0 0
T69 0 12 0 0
T111 0 9 0 0
T112 0 1 0 0
T113 0 6 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T1,T16
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 181412665 4220 0 0
g_div4.Div4Whole_A 181412665 4862 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181412665 4220 0 0
T1 190611 93 0 0
T2 159861 48 0 0
T3 397136 17 0 0
T4 2647 3 0 0
T5 2408 0 0 0
T11 0 5 0 0
T16 940 0 0 0
T17 1010 0 0 0
T18 1264 0 0 0
T19 1156 0 0 0
T20 10859 0 0 0
T68 0 9 0 0
T69 0 6 0 0
T111 0 4 0 0
T112 0 1 0 0
T113 0 5 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181412665 4862 0 0
T1 190611 116 0 0
T2 159861 64 0 0
T3 397136 22 0 0
T4 2647 4 0 0
T5 2408 0 0 0
T11 0 6 0 0
T16 940 0 0 0
T17 1010 0 0 0
T18 1264 0 0 0
T19 1156 0 0 0
T20 10859 0 0 0
T68 0 8 0 0
T69 0 12 0 0
T111 0 6 0 0
T112 0 1 0 0
T113 0 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%