Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	484784289	453	0	0
StatusRise_A	484784289	453	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484784289	453	0	0
T9	245076	0	0	0
T10	119542	0	0	0
T27	32636	0	0	0
T33	1466	4	0	0
T34	926	7	0	0
T35	0	12	0	0
T36	0	5	0	0
T44	0	7	0	0
T66	2128	0	0	0
T75	29973	0	0	0
T111	3990	0	0	0
T112	1608	0	0	0
T113	2984	0	0	0
T116	3248	0	0	0
T117	4782	0	0	0
T166	0	10	0	0
T167	0	10	0	0
T168	0	5	0	0
T169	0	15	0	0
T170	0	19	0	0
T171	0	3	0	0
T172	1823	0	0	0
T173	2006	0	0	0
T174	1480	0	0	0
T175	1849	0	0	0
T176	102669	0	0	0
T177	1354	0	0	0
T178	1683	0	0	0
T179	1766	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484784289	453	0	0
T9	245076	0	0	0
T10	119542	0	0	0
T27	32636	0	0	0
T33	1466	4	0	0
T34	926	7	0	0
T35	0	12	0	0
T36	0	5	0	0
T44	0	7	0	0
T66	2128	0	0	0
T75	29973	0	0	0
T111	3990	0	0	0
T112	1608	0	0	0
T113	2984	0	0	0
T116	3248	0	0	0
T117	4782	0	0	0
T166	0	10	0	0
T167	0	10	0	0
T168	0	5	0	0
T169	0	15	0	0
T170	0	19	0	0
T171	0	3	0	0
T172	1823	0	0	0
T173	2006	0	0	0
T174	1480	0	0	0
T175	1849	0	0	0
T176	102669	0	0	0
T177	1354	0	0	0
T178	1683	0	0	0
T179	1766	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161594763	151	0	0
StatusRise_A	161594763	151	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	151	0	0
T9	122538	0	0	0
T10	59771	0	0	0
T27	16318	0	0	0
T33	733	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	2	0	0
T66	1064	0	0	0
T111	1995	0	0	0
T112	804	0	0	0
T113	1492	0	0	0
T116	1624	0	0	0
T117	2391	0	0	0
T166	0	2	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	5	0	0
T170	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	151	0	0
T9	122538	0	0	0
T10	59771	0	0	0
T27	16318	0	0	0
T33	733	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	2	0	0
T66	1064	0	0	0
T111	1995	0	0	0
T112	804	0	0	0
T113	1492	0	0	0
T116	1624	0	0	0
T117	2391	0	0	0
T166	0	2	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	5	0	0
T170	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161594763	146	0	0
StatusRise_A	161594763	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	146	0	0
T9	122538	0	0	0
T10	59771	0	0	0
T27	16318	0	0	0
T33	733	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T66	1064	0	0	0
T111	1995	0	0	0
T112	804	0	0	0
T113	1492	0	0	0
T116	1624	0	0	0
T117	2391	0	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0
T170	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	146	0	0
T9	122538	0	0	0
T10	59771	0	0	0
T27	16318	0	0	0
T33	733	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T66	1064	0	0	0
T111	1995	0	0	0
T112	804	0	0	0
T113	1492	0	0	0
T116	1624	0	0	0
T117	2391	0	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0
T170	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161594763	156	0	0
StatusRise_A	161594763	156	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	156	0	0
T34	926	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	3	0	0
T75	29973	0	0	0
T166	0	5	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	6	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	1823	0	0	0
T173	2006	0	0	0
T174	1480	0	0	0
T175	1849	0	0	0
T176	102669	0	0	0
T177	1354	0	0	0
T178	1683	0	0	0
T179	1766	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161594763	156	0	0
T34	926	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	3	0	0
T75	29973	0	0	0
T166	0	5	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	6	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	1823	0	0	0
T173	2006	0	0	0
T174	1480	0	0	0
T175	1849	0	0	0
T176	102669	0	0	0
T177	1354	0	0	0
T178	1683	0	0	0
T179	1766	0	0	0