Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50909	0	0
CgEnOn_A	2147483647	41683	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50909	0	0
T1	5790802	414	0	0
T2	4881950	367	0	0
T3	4903692	142	0	0
T4	8980	3	0	0
T5	29564	7	0	0
T9	127649	0	0	0
T10	239090	0	0	0
T16	11806	8	0	0
T17	12772	3	0	0
T18	15752	3	0	0
T19	14552	6	0	0
T20	183558	15	0	0
T21	369440	0	0	0
T27	70946	0	0	0
T33	4450	10	0	0
T34	0	15	0	0
T35	0	20	0	0
T36	0	5	0	0
T44	0	10	0	0
T60	0	1	0	0
T65	0	6	0	0
T66	2171	0	0	0
T111	2079	0	0	0
T112	3355	0	0	0
T113	5743	0	0	0
T116	1692	0	0	0
T117	2391	0	0	0
T166	0	15	0	0
T167	0	15	0	0
T168	0	5	0	0
T169	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41683	0	0
T1	6625192	384	0	0
T2	5604848	334	0	0
T3	6630392	115	0	0
T5	39734	4	0	0
T9	255298	0	0	0
T10	478180	0	0	0
T11	0	31	0	0
T16	15912	5	0	0
T17	17228	0	0	0
T18	21210	0	0	0
T19	19620	3	0	0
T20	255052	0	0	0
T21	710796	0	0	0
T22	0	24	0	0
T27	141892	0	0	0
T33	8900	16	0	0
T34	3175	15	0	0
T35	0	20	0	0
T36	0	5	0	0
T44	0	10	0	0
T65	0	6	0	0
T66	4342	22	0	0
T111	4158	0	0	0
T112	6710	0	0	0
T113	11486	0	0	0
T116	3384	0	0	0
T117	4782	3	0	0
T148	0	32	0	0
T166	0	15	0	0
T167	0	15	0	0
T168	0	5	0	0
T169	0	20	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	181412249	156	0	0
CgEnOn_A	181412249	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181412249	156	0	0
T1	190611	1	0	0
T2	159861	0	0	0
T3	397135	0	0	0
T5	2408	0	0	0
T16	939	0	0	0
T17	1009	0	0	0
T18	1263	0	0	0
T19	1155	0	0	0
T20	10858	0	0	0
T21	28084	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181412249	156	0	0
T1	190611	1	0	0
T2	159861	0	0	0
T3	397135	0	0	0
T5	2408	0	0	0
T16	939	0	0	0
T17	1009	0	0	0
T18	1263	0	0	0
T19	1155	0	0	0
T20	10858	0	0	0
T21	28084	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90705529	156	0	0
CgEnOn_A	90705529	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705529	156	0	0
T1	953038	1	0	0
T2	799302	0	0	0
T3	198565	0	0	0
T5	1204	0	0	0
T16	470	0	0	0
T17	505	0	0	0
T18	632	0	0	0
T19	578	0	0	0
T20	5429	0	0	0
T21	14042	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705529	156	0	0
T1	953038	1	0	0
T2	799302	0	0	0
T3	198565	0	0	0
T5	1204	0	0	0
T16	470	0	0	0
T17	505	0	0	0
T18	632	0	0	0
T19	578	0	0	0
T20	5429	0	0	0
T21	14042	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90705529	156	0	0
CgEnOn_A	90705529	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705529	156	0	0
T1	953038	1	0	0
T2	799302	0	0	0
T3	198565	0	0	0
T5	1204	0	0	0
T16	470	0	0	0
T17	505	0	0	0
T18	632	0	0	0
T19	578	0	0	0
T20	5429	0	0	0
T21	14042	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705529	156	0	0
T1	953038	1	0	0
T2	799302	0	0	0
T3	198565	0	0	0
T5	1204	0	0	0
T16	470	0	0	0
T17	505	0	0	0
T18	632	0	0	0
T19	578	0	0	0
T20	5429	0	0	0
T21	14042	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90705529	156	0	0
CgEnOn_A	90705529	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705529	156	0	0
T1	953038	1	0	0
T2	799302	0	0	0
T3	198565	0	0	0
T5	1204	0	0	0
T16	470	0	0	0
T17	505	0	0	0
T18	632	0	0	0
T19	578	0	0	0
T20	5429	0	0	0
T21	14042	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705529	156	0	0
T1	953038	1	0	0
T2	799302	0	0	0
T3	198565	0	0	0
T5	1204	0	0	0
T16	470	0	0	0
T17	505	0	0	0
T18	632	0	0	0
T19	578	0	0	0
T20	5429	0	0	0
T21	14042	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	364627542	156	0	0
CgEnOn_A	364627542	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364627542	156	0	0
T1	381519	1	0	0
T2	321061	0	0	0
T3	794231	0	0	0
T5	4881	0	0	0
T16	1971	0	0	0
T17	2139	0	0	0
T18	2620	0	0	0
T19	2431	0	0	0
T20	34316	0	0	0
T21	97046	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364627542	149	0	0
T1	381519	1	0	0
T2	321061	0	0	0
T3	794231	0	0	0
T5	4881	0	0	0
T16	1971	0	0	0
T17	2139	0	0	0
T18	2620	0	0	0
T19	2431	0	0	0
T20	34316	0	0	0
T21	97046	0	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	4	0	0
T36	0	1	0	0
T44	0	2	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0
T169	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	390251755	153	0	0
CgEnOn_A	390251755	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	153	0	0
T9	127649	0	0	0
T10	239090	0	0	0
T27	70946	0	0	0
T33	4450	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	2	0	0
T66	2171	0	0	0
T111	2079	0	0	0
T112	3355	0	0	0
T113	5743	0	0	0
T116	1692	0	0	0
T117	2391	0	0	0
T166	0	2	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	5	0	0
T170	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	152	0	0
T9	127649	0	0	0
T10	239090	0	0	0
T27	70946	0	0	0
T33	4450	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	2	0	0
T66	2171	0	0	0
T111	2079	0	0	0
T112	3355	0	0	0
T113	5743	0	0	0
T116	1692	0	0	0
T117	2391	0	0	0
T166	0	2	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	5	0	0
T170	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	390251755	153	0	0
CgEnOn_A	390251755	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	153	0	0
T9	127649	0	0	0
T10	239090	0	0	0
T27	70946	0	0	0
T33	4450	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	2	0	0
T66	2171	0	0	0
T111	2079	0	0	0
T112	3355	0	0	0
T113	5743	0	0	0
T116	1692	0	0	0
T117	2391	0	0	0
T166	0	2	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	5	0	0
T170	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	152	0	0
T9	127649	0	0	0
T10	239090	0	0	0
T27	70946	0	0	0
T33	4450	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	2	0	0
T66	2171	0	0	0
T111	2079	0	0	0
T112	3355	0	0	0
T113	5743	0	0	0
T116	1692	0	0	0
T117	2391	0	0	0
T166	0	2	0	0
T167	0	3	0	0
T168	0	2	0	0
T169	0	5	0	0
T170	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	187276026	160	0	0
CgEnOn_A	187276026	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187276026	160	0	0
T34	3175	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	3	0	0
T75	29361	0	0	0
T166	0	5	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	6	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	3647	0	0	0
T173	3854	0	0	0
T174	1394	0	0	0
T175	3414	0	0	0
T176	96217	0	0	0
T177	1326	0	0	0
T178	1755	0	0	0
T179	3533	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187276026	156	0	0
T34	3175	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T44	0	3	0	0
T75	29361	0	0	0
T166	0	5	0	0
T167	0	4	0	0
T168	0	2	0	0
T169	0	6	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	3647	0	0	0
T173	3854	0	0	0
T174	1394	0	0	0
T175	3414	0	0	0
T176	96217	0	0	0
T177	1326	0	0	0
T178	1755	0	0	0
T179	3533	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90705529	8152	0	0
CgEnOn_A	90705529	5854	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705529	8152	0	0
T1	953038	108	0	0
T2	799302	103	0	0
T3	198565	39	0	0
T4	1323	1	0	0
T5	1204	2	0	0
T16	470	1	0	0
T17	505	1	0	0
T18	632	1	0	0
T19	578	1	0	0
T20	5429	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90705529	5854	0	0
T1	953038	98	0	0
T2	799302	92	0	0
T3	198565	30	0	0
T5	1204	1	0	0
T11	0	10	0	0
T16	470	0	0	0
T17	505	0	0	0
T18	632	0	0	0
T19	578	0	0	0
T20	5429	0	0	0
T21	14042	0	0	0
T22	0	7	0	0
T33	0	2	0	0
T66	0	7	0	0
T117	0	1	0	0
T148	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	181412249	8161	0	0
CgEnOn_A	181412249	5863	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181412249	8161	0	0
T1	190611	113	0	0
T2	159861	103	0	0
T3	397135	41	0	0
T4	2647	1	0	0
T5	2408	2	0	0
T16	939	1	0	0
T17	1009	1	0	0
T18	1263	1	0	0
T19	1155	1	0	0
T20	10858	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181412249	5863	0	0
T1	190611	103	0	0
T2	159861	92	0	0
T3	397135	32	0	0
T5	2408	1	0	0
T11	0	10	0	0
T16	939	0	0	0
T17	1009	0	0	0
T18	1263	0	0	0
T19	1155	0	0	0
T20	10858	0	0	0
T21	28084	0	0	0
T22	0	8	0	0
T33	0	2	0	0
T66	0	7	0	0
T117	0	1	0	0
T148	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	364627542	8241	0	0
CgEnOn_A	364627542	5936	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364627542	8241	0	0
T1	381519	114	0	0
T2	321061	106	0	0
T3	794231	39	0	0
T4	5010	1	0	0
T5	4881	2	0	0
T16	1971	1	0	0
T17	2139	1	0	0
T18	2620	1	0	0
T19	2431	1	0	0
T20	34316	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364627542	5936	0	0
T1	381519	104	0	0
T2	321061	95	0	0
T3	794231	30	0	0
T5	4881	1	0	0
T11	0	11	0	0
T16	1971	0	0	0
T17	2139	0	0	0
T18	2620	0	0	0
T19	2431	0	0	0
T20	34316	0	0	0
T21	97046	0	0	0
T22	0	8	0	0
T33	0	2	0	0
T66	0	8	0	0
T117	0	1	0	0
T148	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	187276026	8200	0	0
CgEnOn_A	187276026	5892	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187276026	8200	0	0
T1	197953	112	0	0
T2	172346	107	0	0
T3	423055	39	0	0
T4	2505	1	0	0
T5	2440	2	0	0
T16	986	1	0	0
T17	1069	1	0	0
T18	1310	1	0	0
T19	1216	1	0	0
T20	17158	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187276026	5892	0	0
T1	197953	101	0	0
T2	172346	96	0	0
T3	423055	30	0	0
T5	2440	1	0	0
T11	0	11	0	0
T14	0	109	0	0
T16	986	0	0	0
T17	1069	0	0	0
T18	1310	0	0	0
T19	1216	0	0	0
T20	17158	0	0	0
T21	48525	0	0	0
T22	0	5	0	0
T66	0	8	0	0
T117	0	1	0	0
T148	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	390251755	4200	0	0
CgEnOn_A	390251755	4199	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	4200	0	0
T1	417195	74	0	0
T2	361449	55	0	0
T3	863350	23	0	0
T5	5085	1	0	0
T16	2053	5	0	0
T17	2228	0	0	0
T18	2729	0	0	0
T19	2534	3	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	1	0	0
T60	0	1	0	0
T65	0	6	0	0
T115	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	4199	0	0
T1	417195	74	0	0
T2	361449	55	0	0
T3	863350	23	0	0
T5	5085	1	0	0
T16	2053	5	0	0
T17	2228	0	0	0
T18	2729	0	0	0
T19	2534	3	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	1	0	0
T60	0	1	0	0
T65	0	6	0	0
T115	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	390251755	4257	0	0
CgEnOn_A	390251755	4256	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	4257	0	0
T1	417195	75	0	0
T2	361449	57	0	0
T3	863350	15	0	0
T5	5085	1	0	0
T16	2053	4	0	0
T17	2228	0	0	0
T18	2729	0	0	0
T19	2534	3	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	4	0	0
T60	0	1	0	0
T65	0	11	0	0
T115	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	4256	0	0
T1	417195	75	0	0
T2	361449	57	0	0
T3	863350	15	0	0
T5	5085	1	0	0
T16	2053	4	0	0
T17	2228	0	0	0
T18	2729	0	0	0
T19	2534	3	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	4	0	0
T60	0	1	0	0
T65	0	11	0	0
T115	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	390251755	4262	0	0
CgEnOn_A	390251755	4261	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	4262	0	0
T1	417195	65	0	0
T2	361449	63	0	0
T3	863350	19	0	0
T5	5085	1	0	0
T16	2053	1	0	0
T17	2228	0	0	0
T18	2729	0	0	0
T19	2534	2	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	2	0	0
T33	0	2	0	0
T65	0	6	0	0
T115	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	4261	0	0
T1	417195	65	0	0
T2	361449	63	0	0
T3	863350	19	0	0
T5	5085	1	0	0
T16	2053	1	0	0
T17	2228	0	0	0
T18	2729	0	0	0
T19	2534	2	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	2	0	0
T33	0	2	0	0
T65	0	6	0	0
T115	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T16
1	1	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	390251755	4190	0	0
CgEnOn_A	390251755	4189	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	4190	0	0
T1	417195	70	0	0
T2	361449	58	0	0
T3	863350	19	0	0
T5	5085	1	0	0
T16	2053	4	0	0
T17	2228	0	0	0
T18	2729	0	0	0
T19	2534	4	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	3	0	0
T60	0	1	0	0
T65	0	11	0	0
T115	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390251755	4189	0	0
T1	417195	70	0	0
T2	361449	58	0	0
T3	863350	19	0	0
T5	5085	1	0	0
T16	2053	4	0	0
T17	2228	0	0	0
T18	2729	0	0	0
T19	2534	4	0	0
T20	35747	0	0	0
T21	101092	0	0	0
T22	0	3	0	0
T60	0	1	0	0
T65	0	11	0	0
T115	0	1	0	0