Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T1,T17
0	1	Covered	T1,T2,T59
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T36
1	0	Covered	T22,T17,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1094364966	13931	0	0
GateOpen_A	1094364966	20658	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094364966	13931	0	0
T1	1766734	83	0	0
T2	1530379	155	0	0
T3	483094	0	0	0
T8	0	54	0	0
T10	0	86	0	0
T11	0	183	0	0
T15	12080	0	0	0
T16	11108	0	0	0
T17	2558	8	0	0
T18	14985	0	0	0
T19	4090	0	0	0
T20	4825	0	0	0
T22	4663	4	0	0
T36	0	4	0	0
T58	0	1	0	0
T59	0	22	0	0
T95	0	1	0	0
T96	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094364966	20658	0	0
T1	1766734	87	0	0
T2	1530379	183	0	0
T4	181586	0	0	0
T5	24704	4	0	0
T6	6591	0	0	0
T15	12080	4	0	0
T16	11108	4	0	0
T17	2558	12	0	0
T18	14985	4	0	0
T19	0	4	0	0
T20	0	4	0	0
T22	4663	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T1,T17
0	1	Covered	T1,T2,T59
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T36
1	0	Covered	T22,T17,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	120843892	3304	0	0
GateOpen_A	120843892	4983	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843892	3304	0	0
T1	489009	16	0	0
T2	169536	35	0	0
T3	53654	0	0	0
T8	0	13	0	0
T10	0	26	0	0
T11	0	54	0	0
T15	1462	0	0	0
T16	1221	0	0	0
T17	272	2	0	0
T18	1833	0	0	0
T19	467	0	0	0
T20	518	0	0	0
T22	508	1	0	0
T36	0	1	0	0
T59	0	5	0	0
T96	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843892	4983	0	0
T1	489009	17	0	0
T2	169536	42	0	0
T4	20801	0	0	0
T5	2913	1	0	0
T6	715	0	0	0
T15	1462	1	0	0
T16	1221	1	0	0
T17	272	3	0	0
T18	1833	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	508	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T1,T17
0	1	Covered	T1,T2,T59
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T36
1	0	Covered	T22,T17,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	241688596	3547	0	0
GateOpen_A	241688596	5226	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241688596	3547	0	0
T1	978027	24	0	0
T2	339075	40	0	0
T3	107308	0	0	0
T8	0	13	0	0
T10	0	30	0	0
T11	0	65	0	0
T15	2927	0	0	0
T16	2442	0	0	0
T17	543	2	0	0
T18	3669	0	0	0
T19	935	0	0	0
T20	1036	0	0	0
T22	1015	1	0	0
T36	0	1	0	0
T59	0	5	0	0
T96	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241688596	5226	0	0
T1	978027	25	0	0
T2	339075	47	0	0
T4	41601	0	0	0
T5	5828	1	0	0
T6	1429	0	0	0
T15	2927	1	0	0
T16	2442	1	0	0
T17	543	3	0	0
T18	3669	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	1015	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T1,T17
0	1	Covered	T1,T2,T59
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T36
1	0	Covered	T22,T17,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	484410189	3562	0	0
GateOpen_A	484410189	5246	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484410189	3562	0	0
T1	196589	22	0	0
T2	678864	42	0	0
T3	214751	0	0	0
T8	0	14	0	0
T15	5127	0	0	0
T16	4963	0	0	0
T17	1137	2	0	0
T18	6322	0	0	0
T19	1792	0	0	0
T20	2181	0	0	0
T22	2095	1	0	0
T36	0	1	0	0
T58	0	1	0	0
T59	0	5	0	0
T95	0	1	0	0
T96	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484410189	5246	0	0
T1	196589	23	0	0
T2	678864	49	0	0
T4	83294	0	0	0
T5	10642	1	0	0
T6	2965	0	0	0
T15	5127	1	0	0
T16	4963	1	0	0
T17	1137	3	0	0
T18	6322	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	2095	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T22,T1,T17
0	1	Covered	T1,T2,T59
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T36
1	0	Covered	T22,T17,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	247422289	3518	0	0
GateOpen_A	247422289	5203	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247422289	3518	0	0
T1	103109	21	0	0
T2	342904	38	0	0
T3	107381	0	0	0
T8	0	14	0	0
T10	0	30	0	0
T11	0	64	0	0
T15	2564	0	0	0
T16	2482	0	0	0
T17	606	2	0	0
T18	3161	0	0	0
T19	896	0	0	0
T20	1090	0	0	0
T22	1045	1	0	0
T36	0	1	0	0
T59	0	7	0	0
T96	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247422289	5203	0	0
T1	103109	22	0	0
T2	342904	45	0	0
T4	35890	0	0	0
T5	5321	1	0	0
T6	1482	0	0	0
T15	2564	1	0	0
T16	2482	1	0	0
T17	606	3	0	0
T18	3161	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	1045	2	0	0