Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	839683080	68261	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839683080	68261	0	0
T1	1087845	830	0	0
T2	1723160	873	0	0
T3	1073750	188	0	0
T8	0	497	0	0
T9	0	316	0	0
T10	0	302	0	0
T11	0	639	0	0
T12	0	44	0	0
T13	0	1154	0	0
T14	0	687	0	0
T15	7210	0	0	0
T16	6455	0	0	0
T17	6570	0	0	0
T18	7575	0	0	0
T19	4850	0	0	0
T20	5565	0	0	0
T21	5670	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167936616	10142	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	10142	0	0
T1	217569	108	0	0
T2	344632	125	0	0
T3	214750	28	0	0
T8	0	65	0	0
T9	0	41	0	0
T10	0	44	0	0
T11	0	85	0	0
T12	0	8	0	0
T13	0	149	0	0
T14	0	129	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T21	1134	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167936616	10000	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	10000	0	0
T1	217569	105	0	0
T2	344632	123	0	0
T3	214750	23	0	0
T8	0	62	0	0
T9	0	41	0	0
T10	0	38	0	0
T11	0	83	0	0
T12	0	8	0	0
T13	0	167	0	0
T14	0	129	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T21	1134	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167936616	13678	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	13678	0	0
T1	217569	170	0	0
T2	344632	196	0	0
T3	214750	37	0	0
T8	0	102	0	0
T9	0	62	0	0
T10	0	60	0	0
T11	0	129	0	0
T12	0	8	0	0
T13	0	229	0	0
T14	0	134	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T21	1134	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167936616	13702	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	13702	0	0
T1	217569	170	0	0
T2	344632	170	0	0
T3	214750	40	0	0
T8	0	102	0	0
T9	0	64	0	0
T10	0	62	0	0
T11	0	127	0	0
T12	0	9	0	0
T13	0	231	0	0
T14	0	130	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T21	1134	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167936616	20739	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	20739	0	0
T1	217569	277	0	0
T2	344632	259	0	0
T3	214750	60	0	0
T8	0	166	0	0
T9	0	108	0	0
T10	0	98	0	0
T11	0	215	0	0
T12	0	11	0	0
T13	0	378	0	0
T14	0	165	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T21	1134	0	0	0