Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T1,T2,T25

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	167936616	165115719	0	0
AllClkBypReqTrue_A	167936616	132782	0	0
IoClkBypReqFalse_A	167936616	165032490	0	2412
IoClkBypReqTrue_A	167936616	211323	0	0
LcClkBypAckFalse_A	167936616	165122972	0	0
LcClkBypAckTrue_A	167936616	125529	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	165115719	0	0
T1	217569	215543	0	0
T2	344632	343087	0	0
T4	21691	21659	0	0
T5	2659	2588	0	0
T6	1049	986	0	0
T15	1442	1281	0	0
T16	1291	1256	0	0
T17	1314	1159	0	0
T18	1515	1308	0	0
T22	1117	1025	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	132782	0	0
T1	217569	839	0	0
T2	344632	2103	0	0
T4	21691	0	0	0
T5	2659	44	0	0
T6	1049	0	0	0
T8	0	675	0	0
T15	1442	119	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	174	0	0
T19	0	99	0	0
T20	0	17	0	0
T22	1117	0	0	0
T25	0	226	0	0
T73	0	128	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	165032490	0	2412
T1	217569	215472	0	3
T2	344632	343014	0	3
T4	21691	21657	0	3
T5	2659	1907	0	3
T6	1049	984	0	3
T15	1442	1179	0	3
T16	1291	1254	0	3
T17	1314	1157	0	3
T18	1515	1154	0	3
T22	1117	1023	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	211323	0	0
T1	217569	1538	0	0
T2	344632	2815	0	0
T4	21691	0	0	0
T5	2659	723	0	0
T6	1049	0	0	0
T8	0	1180	0	0
T15	1442	219	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	326	0	0
T19	0	84	0	0
T22	1117	0	0	0
T25	0	321	0	0
T73	0	239	0	0
T94	0	212	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	165122972	0	0
T1	217569	215529	0	0
T2	344632	343101	0	0
T4	21691	21659	0	0
T5	2659	2389	0	0
T6	1049	986	0	0
T15	1442	1292	0	0
T16	1291	1256	0	0
T17	1314	1159	0	0
T18	1515	1265	0	0
T22	1117	1025	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	125529	0	0
T1	217569	982	0	0
T2	344632	1961	0	0
T4	21691	0	0	0
T5	2659	243	0	0
T6	1049	0	0	0
T8	0	947	0	0
T15	1442	108	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	217	0	0
T19	0	73	0	0
T22	1117	0	0	0
T25	0	245	0	0
T73	0	105	0	0
T94	0	133	0	0