Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2061976436	14542	0	0
TransStop_A	2061976436	7460	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2061976436	14542	0	0
T1	871232	235	0	0
T2	2857740	212	0	0
T3	223706	0	0	0
T4	224307	0	0	0
T6	9267	7	0	0
T8	0	65	0	0
T10	0	11	0	0
T15	21364	0	0	0
T16	20676	0	0	0
T17	4896	0	0	0
T18	26344	0	0	0
T19	7468	0	0	0
T20	2271	0	0	0
T21	6679	11	0	0
T22	6612	0	0	0
T25	0	40	0	0
T36	0	4	0	0
T58	0	4	0	0
T95	0	4	0	0
T96	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2061976436	7460	0	0
T1	871232	120	0	0
T2	2857740	124	0	0
T3	447412	0	0	0
T4	149538	0	0	0
T6	6178	3	0	0
T8	0	23	0	0
T10	0	17	0	0
T15	21364	0	0	0
T16	20676	0	0	0
T17	4896	0	0	0
T18	26344	0	0	0
T19	7468	0	0	0
T20	4542	0	0	0
T21	13358	4	0	0
T22	4408	0	0	0
T25	0	11	0	0
T36	0	4	0	0
T58	0	4	0	0
T95	0	4	0	0
T96	0	4	0	0
T97	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	515494109	3622	0	0
TransStop_A	515494109	1873	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515494109	3622	0	0
T1	217808	61	0	0
T2	714435	50	0	0
T4	74769	0	0	0
T6	3089	4	0	0
T8	0	11	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1224	0	0	0
T18	6586	0	0	0
T19	1867	0	0	0
T21	0	3	0	0
T22	2204	0	0	0
T25	0	11	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515494109	1873	0	0
T1	217808	32	0	0
T2	714435	27	0	0
T4	74769	0	0	0
T6	3089	2	0	0
T8	0	5	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1224	0	0	0
T18	6586	0	0	0
T19	1867	0	0	0
T21	0	2	0	0
T22	2204	0	0	0
T25	0	4	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	515494109	3651	0	0
TransStop_A	515494109	1881	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515494109	3651	0	0
T1	217808	61	0	0
T2	714435	51	0	0
T4	74769	0	0	0
T6	3089	1	0	0
T8	0	16	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1224	0	0	0
T18	6586	0	0	0
T19	1867	0	0	0
T21	0	2	0	0
T22	2204	0	0	0
T25	0	9	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515494109	1881	0	0
T1	217808	29	0	0
T2	714435	33	0	0
T3	223706	0	0	0
T8	0	6	0	0
T10	0	8	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1224	0	0	0
T18	6586	0	0	0
T19	1867	0	0	0
T20	2271	0	0	0
T21	6679	1	0	0
T25	0	1	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	515494109	3702	0	0
TransStop_A	515494109	1914	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515494109	3702	0	0
T1	217808	59	0	0
T2	714435	56	0	0
T4	74769	0	0	0
T6	3089	2	0	0
T8	0	20	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1224	0	0	0
T18	6586	0	0	0
T19	1867	0	0	0
T21	0	3	0	0
T22	2204	0	0	0
T25	0	12	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515494109	1914	0	0
T1	217808	29	0	0
T2	714435	30	0	0
T4	74769	0	0	0
T6	3089	1	0	0
T8	0	6	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1224	0	0	0
T18	6586	0	0	0
T19	1867	0	0	0
T21	0	1	0	0
T22	2204	0	0	0
T25	0	4	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	515494109	3567	0	0
TransStop_A	515494109	1792	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515494109	3567	0	0
T1	217808	54	0	0
T2	714435	55	0	0
T3	223706	0	0	0
T8	0	18	0	0
T10	0	11	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1224	0	0	0
T18	6586	0	0	0
T19	1867	0	0	0
T20	2271	0	0	0
T21	6679	3	0	0
T25	0	8	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515494109	1792	0	0
T1	217808	30	0	0
T2	714435	34	0	0
T3	223706	0	0	0
T8	0	6	0	0
T10	0	9	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1224	0	0	0
T18	6586	0	0	0
T19	1867	0	0	0
T20	2271	0	0	0
T21	6679	0	0	0
T25	0	2	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	7	0	0