Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	167936616	20216062	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	20216062	0	57
T1	217569	96700	0	0
T2	344632	751467	0	0
T3	214750	24233	0	1
T8	0	55568	0	0
T9	0	36572	0	1
T10	0	35025	0	0
T11	0	71500	0	0
T12	0	2316	0	1
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T21	1134	0	0	0
T23	0	898	0	1
T24	0	950	0	1
T29	0	0	0	1
T98	0	0	0	1
T99	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1