Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_pulse_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div2_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_io_div4_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_main_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00
tb.dut.u_usb_meas.u_meas.u_sync_ref 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_div2_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_div2_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_div4_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_div4_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_main_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_main_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_usb_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_usb_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 66.67 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Module : prim_pulse_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Module : prim_pulse_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Module : prim_pulse_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 2147483647 899884 0 0
SrcPulseCheck_M 2147483647 898402 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 899884 0 0
T1 4055055 3921 0 0
T2 2924692 3386 0 0
T3 1028784 518 0 0
T4 325356 462 0 0
T8 0 2893 0 0
T9 0 248 0 0
T10 0 1648 0 0
T15 22153 0 0 0
T16 19966 0 0 0
T17 5574 0 0 0
T18 27258 0 0 0
T19 7899 0 0 0
T22 8963 0 0 0
T23 0 60 0 0
T24 0 128 0 0
T25 0 660 0 0
T26 0 50 0 0
T27 0 190 0 0
T48 14622 3 0 0
T49 20458 1 0 0
T50 10516 1 0 0
T54 2470 1 0 0
T55 22450 1 0 0
T102 20518 1 0 0
T103 26936 1 0 0
T104 19712 1 0 0
T105 12532 2 0 0
T106 6646 0 0 0
T107 4315 0 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 898402 0 0
T1 1574663 3921 0 0
T2 2238878 3270 0 0
T3 538652 518 0 0
T4 85703 462 0 0
T8 0 2893 0 0
T9 0 248 0 0
T10 0 1648 0 0
T15 7303 0 0 0
T16 6467 0 0 0
T17 3535 0 0 0
T18 8542 0 0 0
T19 3395 0 0 0
T22 3872 0 0 0
T23 0 60 0 0
T24 0 128 0 0
T25 0 660 0 0
T26 0 50 0 0
T27 0 190 0 0
T48 52012 3 0 0
T49 18704 1 0 0
T50 4394 1 0 0
T54 4582 1 0 0
T55 9014 1 0 0
T102 7734 1 0 0
T103 25562 1 0 0
T104 13180 1 0 0
T105 20714 2 0 0
T106 2820 0 0 0
T107 12640 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 487596680 23679 0 0
SrcPulseCheck_M 168943355 23679 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 487596680 23679 0 0
T1 196589 191 0 0
T2 678864 205 0 0
T3 214750 38 0 0
T4 83294 14 0 0
T8 0 138 0 0
T15 5127 0 0 0
T16 4962 0 0 0
T17 1137 0 0 0
T18 6321 0 0 0
T19 1791 0 0 0
T22 2094 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 23679 0 0
T1 217569 191 0 0
T2 344632 205 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 138 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 487596680 29546 0 0
SrcPulseCheck_M 168943355 29564 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 487596680 29546 0 0
T1 196589 197 0 0
T2 678864 215 0 0
T3 214750 38 0 0
T4 83294 14 0 0
T8 0 142 0 0
T15 5127 0 0 0
T16 4962 0 0 0
T17 1137 0 0 0
T18 6321 0 0 0
T19 1791 0 0 0
T22 2094 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29564 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 29532 0 0
SrcPulseCheck_M 487596680 29549 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29532 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 487596680 29549 0 0
T1 196589 197 0 0
T2 678864 215 0 0
T3 214750 38 0 0
T4 83294 14 0 0
T8 0 142 0 0
T15 5127 0 0 0
T16 4962 0 0 0
T17 1137 0 0 0
T18 6321 0 0 0
T19 1791 0 0 0
T22 2094 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 243234822 23679 0 0
SrcPulseCheck_M 168943355 23679 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 243234822 23679 0 0
T1 978027 191 0 0
T2 339075 205 0 0
T3 107308 38 0 0
T4 41601 14 0 0
T8 0 138 0 0
T15 2927 0 0 0
T16 2441 0 0 0
T17 543 0 0 0
T18 3668 0 0 0
T19 935 0 0 0
T22 1014 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 23679 0 0
T1 217569 191 0 0
T2 344632 205 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 138 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 243234822 29625 0 0
SrcPulseCheck_M 168943355 29648 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 243234822 29625 0 0
T1 978027 197 0 0
T2 339075 215 0 0
T3 107308 38 0 0
T4 41601 14 0 0
T8 0 142 0 0
T15 2927 0 0 0
T16 2441 0 0 0
T17 543 0 0 0
T18 3668 0 0 0
T19 935 0 0 0
T22 1014 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29648 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 29617 0 0
SrcPulseCheck_M 243234822 29630 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29617 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 243234822 29630 0 0
T1 978027 197 0 0
T2 339075 215 0 0
T3 107308 38 0 0
T4 41601 14 0 0
T8 0 142 0 0
T15 2927 0 0 0
T16 2441 0 0 0
T17 543 0 0 0
T18 3668 0 0 0
T19 935 0 0 0
T22 1014 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 121616803 23679 0 0
SrcPulseCheck_M 168943355 23679 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 121616803 23679 0 0
T1 489008 191 0 0
T2 169536 205 0 0
T3 53654 38 0 0
T4 20800 14 0 0
T8 0 138 0 0
T15 1462 0 0 0
T16 1221 0 0 0
T17 271 0 0 0
T18 1833 0 0 0
T19 467 0 0 0
T22 507 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 23679 0 0
T1 217569 191 0 0
T2 344632 205 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 138 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 121616803 29594 0 0
SrcPulseCheck_M 168943355 29641 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 121616803 29594 0 0
T1 489008 197 0 0
T2 169536 215 0 0
T3 53654 38 0 0
T4 20800 14 0 0
T8 0 142 0 0
T15 1462 0 0 0
T16 1221 0 0 0
T17 271 0 0 0
T18 1833 0 0 0
T19 467 0 0 0
T22 507 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29641 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 29594 0 0
SrcPulseCheck_M 121616803 29599 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29594 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 121616803 29599 0 0
T1 489008 197 0 0
T2 169536 215 0 0
T3 53654 38 0 0
T4 20800 14 0 0
T8 0 142 0 0
T15 1462 0 0 0
T16 1221 0 0 0
T17 271 0 0 0
T18 1833 0 0 0
T19 467 0 0 0
T22 507 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 518813495 23679 0 0
SrcPulseCheck_M 168943355 23679 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 518813495 23679 0 0
T1 217808 191 0 0
T2 714435 205 0 0
T3 223706 38 0 0
T4 74768 14 0 0
T8 0 138 0 0
T15 5341 0 0 0
T16 5169 0 0 0
T17 1223 0 0 0
T18 6585 0 0 0
T19 1866 0 0 0
T22 2203 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 23679 0 0
T1 217569 191 0 0
T2 344632 205 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 138 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 518813495 29579 0 0
SrcPulseCheck_M 168943355 29597 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 518813495 29579 0 0
T1 217808 197 0 0
T2 714435 215 0 0
T3 223706 38 0 0
T4 74768 14 0 0
T8 0 142 0 0
T15 5341 0 0 0
T16 5169 0 0 0
T17 1223 0 0 0
T18 6585 0 0 0
T19 1866 0 0 0
T22 2203 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29597 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 29571 0 0
SrcPulseCheck_M 518813495 29582 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29571 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 518813495 29582 0 0
T1 217808 197 0 0
T2 714435 215 0 0
T3 223706 38 0 0
T4 74768 14 0 0
T8 0 142 0 0
T15 5341 0 0 0
T16 5169 0 0 0
T17 1223 0 0 0
T18 6585 0 0 0
T19 1866 0 0 0
T22 2203 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 249015369 23229 0 0
SrcPulseCheck_M 168943355 23679 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 249015369 23229 0 0
T1 103109 191 0 0
T2 342904 205 0 0
T3 107380 38 0 0
T4 35889 14 0 0
T8 0 138 0 0
T15 2563 0 0 0
T16 2481 0 0 0
T17 605 0 0 0
T18 3161 0 0 0
T19 896 0 0 0
T22 1045 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 6 0 0
T27 0 19 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 23679 0 0
T1 217569 191 0 0
T2 344632 205 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 138 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 10 0 0
T27 0 38 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 249015369 29554 0 0
SrcPulseCheck_M 168943355 29763 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 249015369 29554 0 0
T1 103109 197 0 0
T2 342904 215 0 0
T3 107380 38 0 0
T4 35889 14 0 0
T8 0 142 0 0
T15 2563 0 0 0
T16 2481 0 0 0
T17 605 0 0 0
T18 3161 0 0 0
T19 896 0 0 0
T22 1045 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 57 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29763 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 76 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 29443 0 0
SrcPulseCheck_M 249015369 29591 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 29443 0 0
T1 217569 197 0 0
T2 344632 215 0 0
T3 214750 38 0 0
T4 21691 14 0 0
T8 0 142 0 0
T15 1442 0 0 0
T16 1291 0 0 0
T17 1314 0 0 0
T18 1515 0 0 0
T19 970 0 0 0
T22 1117 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 57 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 249015369 29591 0 0
T1 103109 197 0 0
T2 342904 215 0 0
T3 107380 38 0 0
T4 35889 14 0 0
T8 0 142 0 0
T15 2563 0 0 0
T16 2481 0 0 0
T17 605 0 0 0
T18 3161 0 0 0
T19 896 0 0 0
T22 1045 0 0 0
T23 0 4 0 0
T24 0 8 0 0
T25 0 24 0 0
T26 0 20 0 0
T27 0 65 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT49,T53,T54
10CoveredT49,T53,T54
11CoveredT53,T55,T108

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT49,T53,T54
10CoveredT53,T55,T108
11CoveredT49,T53,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 36 0 0
SrcPulseCheck_M 487596680 36 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 36 0 0
T49 10229 1 0 0
T53 5915 3 0 0
T54 2470 2 0 0
T55 11225 3 0 0
T102 10259 3 0 0
T104 9856 1 0 0
T105 6266 2 0 0
T106 6646 1 0 0
T108 1752 2 0 0
T109 6484 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 487596680 36 0 0
T49 20459 1 0 0
T53 22712 3 0 0
T54 9881 2 0 0
T55 10775 3 0 0
T102 9848 3 0 0
T104 15019 1 0 0
T105 22278 2 0 0
T106 6646 1 0 0
T108 12939 2 0 0
T109 6224 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT49,T53,T54
10CoveredT49,T53,T54
11CoveredT55,T108,T102

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT49,T53,T54
10CoveredT55,T108,T102
11CoveredT49,T53,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 30 0 0
SrcPulseCheck_M 487596680 30 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 30 0 0
T49 10229 1 0 0
T53 5915 2 0 0
T54 2470 1 0 0
T55 11225 3 0 0
T102 10259 3 0 0
T104 9856 1 0 0
T105 6266 2 0 0
T106 6646 1 0 0
T108 1752 2 0 0
T110 6178 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 487596680 30 0 0
T49 20459 1 0 0
T53 22712 2 0 0
T54 9881 1 0 0
T55 10775 3 0 0
T102 9848 3 0 0
T104 15019 1 0 0
T105 22278 2 0 0
T106 6646 1 0 0
T108 12939 2 0 0
T110 65909 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T50
10CoveredT48,T49,T50
11CoveredT105,T107

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T50
10CoveredT105,T107
11CoveredT48,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 26 0 0
SrcPulseCheck_M 243234822 26 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 26 0 0
T48 7311 3 0 0
T49 10229 1 0 0
T50 5258 1 0 0
T54 2470 1 0 0
T55 11225 1 0 0
T102 10259 1 0 0
T103 13468 1 0 0
T104 9856 1 0 0
T105 6266 2 0 0
T107 4315 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 243234822 26 0 0
T48 26006 3 0 0
T49 9352 1 0 0
T50 2197 1 0 0
T54 4582 1 0 0
T55 4507 1 0 0
T102 3867 1 0 0
T103 12781 1 0 0
T104 6590 1 0 0
T105 10357 2 0 0
T107 12640 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T50
10CoveredT48,T49,T50
11CoveredT105,T107

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T50
10CoveredT105,T107
11CoveredT48,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 23 0 0
SrcPulseCheck_M 243234822 23 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 23 0 0
T48 7311 2 0 0
T49 10229 1 0 0
T50 5258 1 0 0
T55 11225 2 0 0
T102 10259 1 0 0
T103 13468 1 0 0
T104 9856 2 0 0
T105 6266 2 0 0
T106 6646 1 0 0
T109 6484 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 243234822 23 0 0
T48 26006 2 0 0
T49 9352 1 0 0
T50 2197 1 0 0
T55 4507 2 0 0
T102 3867 1 0 0
T103 12781 1 0 0
T104 6590 2 0 0
T105 10357 2 0 0
T106 2820 1 0 0
T109 2887 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T50
10CoveredT48,T49,T50
11CoveredT49,T50,T55

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T50
10CoveredT49,T50,T55
11CoveredT48,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 30 0 0
SrcPulseCheck_M 121616803 30 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 30 0 0
T48 7311 1 0 0
T49 10229 2 0 0
T50 5258 4 0 0
T51 4114 2 0 0
T53 5915 1 0 0
T55 11225 2 0 0
T102 10259 1 0 0
T103 13468 2 0 0
T104 9856 2 0 0
T105 6266 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 121616803 30 0 0
T48 13004 1 0 0
T49 4675 2 0 0
T50 1100 4 0 0
T51 1860 2 0 0
T53 5303 1 0 0
T55 2253 2 0 0
T102 1935 1 0 0
T103 6389 2 0 0
T104 3295 2 0 0
T105 5176 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T50
10CoveredT48,T49,T50
11CoveredT49,T50,T55

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T50
10CoveredT49,T50,T55
11CoveredT48,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 28 0 0
SrcPulseCheck_M 121616803 28 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 28 0 0
T48 7311 1 0 0
T49 10229 2 0 0
T50 5258 2 0 0
T51 4114 1 0 0
T53 5915 1 0 0
T55 11225 3 0 0
T102 10259 1 0 0
T103 13468 1 0 0
T104 9856 1 0 0
T108 1752 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 121616803 28 0 0
T48 13004 1 0 0
T49 4675 2 0 0
T50 1100 2 0 0
T51 1860 1 0 0
T53 5303 1 0 0
T55 2253 3 0 0
T102 1935 1 0 0
T103 6389 1 0 0
T104 3295 1 0 0
T108 3102 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT49,T52,T53
10CoveredT49,T52,T53
11CoveredT49

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT49,T52,T53
10CoveredT49
11CoveredT49,T52,T53

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 26 0 0
SrcPulseCheck_M 518813495 26 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 26 0 0
T49 10229 3 0 0
T51 4114 1 0 0
T52 10905 1 0 0
T53 5915 1 0 0
T54 2470 1 0 0
T55 11225 2 0 0
T102 10259 1 0 0
T103 13468 1 0 0
T104 9856 3 0 0
T108 1752 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 518813495 26 0 0
T49 21312 3 0 0
T51 8572 1 0 0
T52 136320 1 0 0
T53 23660 1 0 0
T54 10293 1 0 0
T55 11225 2 0 0
T102 10259 1 0 0
T103 28060 1 0 0
T104 15646 3 0 0
T108 13480 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T53
10CoveredT48,T49,T53
11CoveredT49,T110

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T53
10CoveredT49,T110
11CoveredT48,T49,T53

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 32 0 0
SrcPulseCheck_M 518813495 32 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 32 0 0
T48 7311 1 0 0
T49 10229 4 0 0
T51 4114 1 0 0
T53 5915 1 0 0
T54 2470 1 0 0
T55 11225 2 0 0
T102 10259 1 0 0
T103 13468 1 0 0
T106 6646 2 0 0
T108 1752 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 518813495 32 0 0
T48 56240 1 0 0
T49 21312 4 0 0
T51 8572 1 0 0
T53 23660 1 0 0
T54 10293 1 0 0
T55 11225 2 0 0
T102 10259 1 0 0
T103 28060 1 0 0
T106 6924 2 0 0
T108 13480 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T54
10CoveredT48,T49,T54
11CoveredT48,T111

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T54
10CoveredT48,T111
11CoveredT48,T49,T54

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 31 0 0
SrcPulseCheck_M 249015369 31 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 31 0 0
T48 7311 5 0 0
T49 10229 2 0 0
T54 2470 1 0 0
T55 11225 2 0 0
T102 10259 1 0 0
T104 9856 1 0 0
T105 6266 1 0 0
T106 6646 3 0 0
T108 1752 1 0 0
T112 12414 2 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 249015369 31 0 0
T48 26995 5 0 0
T49 10229 2 0 0
T54 4941 1 0 0
T55 5388 2 0 0
T102 4924 1 0 0
T104 7510 1 0 0
T105 11139 1 0 0
T106 3323 3 0 0
T108 6470 1 0 0
T112 12414 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T53
10CoveredT48,T49,T53
11CoveredT48,T113,T111

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT48,T49,T53
10CoveredT48,T113,T111
11CoveredT48,T49,T53

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 168943355 35 0 0
SrcPulseCheck_M 249015369 35 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168943355 35 0 0
T48 7311 4 0 0
T49 10229 1 0 0
T53 5915 1 0 0
T55 11225 2 0 0
T102 10259 1 0 0
T104 9856 1 0 0
T106 6646 1 0 0
T108 1752 2 0 0
T113 5419 2 0 0
T114 5971 1 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 249015369 35 0 0
T48 26995 4 0 0
T49 10229 1 0 0
T53 11357 1 0 0
T55 5388 2 0 0
T102 4924 1 0 0
T104 7510 1 0 0
T106 3323 1 0 0
T108 6470 2 0 0
T113 2738 2 0 0
T114 2866 1 0 0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 484409743 90200 0 0
SrcPulseCheck_M 18786411 89551 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 484409743 90200 0 0
T1 196589 771 0 0
T2 678864 651 0 0
T3 214750 101 0 0
T4 83294 111 0 0
T8 0 552 0 0
T9 0 62 0 0
T10 0 355 0 0
T15 5127 0 0 0
T16 4962 0 0 0
T17 1137 0 0 0
T18 6321 0 0 0
T19 1791 0 0 0
T22 2094 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 135 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 18786411 89551 0 0
T1 40309 771 0 0
T2 323151 651 0 0
T3 461 101 0 0
T4 186 111 0 0
T8 0 552 0 0
T9 0 62 0 0
T10 0 355 0 0
T15 373 0 0 0
T16 361 0 0 0
T17 91 0 0 0
T18 461 0 0 0
T19 130 0 0 0
T22 156 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 135 0 0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 241688221 89741 0 0
SrcPulseCheck_M 18786411 89093 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241688221 89741 0 0
T1 978027 771 0 0
T2 339075 651 0 0
T3 107308 101 0 0
T4 41601 111 0 0
T8 0 552 0 0
T9 0 62 0 0
T10 0 355 0 0
T15 2927 0 0 0
T16 2441 0 0 0
T17 543 0 0 0
T18 3668 0 0 0
T19 935 0 0 0
T22 1014 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 135 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 18786411 89093 0 0
T1 40309 771 0 0
T2 323151 651 0 0
T3 461 101 0 0
T4 186 111 0 0
T8 0 552 0 0
T9 0 62 0 0
T10 0 355 0 0
T15 373 0 0 0
T16 361 0 0 0
T17 91 0 0 0
T18 461 0 0 0
T19 130 0 0 0
T22 156 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 135 0 0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 120843490 88529 0 0
SrcPulseCheck_M 18786411 87887 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 120843490 88529 0 0
T1 489008 771 0 0
T2 169536 647 0 0
T3 53654 101 0 0
T4 20800 111 0 0
T8 0 552 0 0
T9 0 62 0 0
T10 0 355 0 0
T15 1462 0 0 0
T16 1221 0 0 0
T17 271 0 0 0
T18 1833 0 0 0
T19 467 0 0 0
T22 507 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 135 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 18786411 87887 0 0
T1 40309 771 0 0
T2 323151 647 0 0
T3 461 101 0 0
T4 186 111 0 0
T8 0 552 0 0
T9 0 62 0 0
T10 0 355 0 0
T15 373 0 0 0
T16 361 0 0 0
T17 91 0 0 0
T18 461 0 0 0
T19 130 0 0 0
T22 156 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 135 0 0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 515493652 109211 0 0
SrcPulseCheck_M 18961672 109101 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 515493652 109211 0 0
T1 217808 1023 0 0
T2 714435 802 0 0
T3 223706 101 0 0
T4 74768 87 0 0
T8 0 815 0 0
T9 0 62 0 0
T10 0 583 0 0
T15 5341 0 0 0
T16 5169 0 0 0
T17 1223 0 0 0
T18 6585 0 0 0
T19 1866 0 0 0
T22 2203 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 183 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 18961672 109101 0 0
T1 40571 1023 0 0
T2 241086 686 0 0
T3 461 101 0 0
T4 162 87 0 0
T8 0 815 0 0
T9 0 62 0 0
T10 0 583 0 0
T15 373 0 0 0
T16 361 0 0 0
T17 91 0 0 0
T18 461 0 0 0
T19 130 0 0 0
T22 156 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 183 0 0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS3133100.00
CONT_ASSIGN4900
CONT_ASSIGN5200
ALWAYS5500
ALWAYS8933100.00
CONT_ASSIGN9711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
32 1 1
34 1 1
49 unreachable
52 unreachable
55 unreachable
56 unreachable
58 unreachable
89 1 1
90 1 1
92 1 1
97 1 1


Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT5,T6,T4
01CoveredT4,T1,T2
10CoveredT4,T1,T2
11CoveredT4,T1,T2

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 31 2 2 100.00
IF 89 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 31 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


LineNo. Expression -1-: 89 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T4
0 Covered T5,T6,T4


Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DstPulseCheck_A 247421867 108306 0 0
SrcPulseCheck_M 19070296 107914 0 0


DstPulseCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 247421867 108306 0 0
T1 103109 963 0 0
T2 342904 786 0 0
T3 107380 101 0 0
T4 35889 87 0 0
T8 0 729 0 0
T9 0 62 0 0
T10 0 583 0 0
T15 2563 0 0 0
T16 2481 0 0 0
T17 605 0 0 0
T18 3161 0 0 0
T19 896 0 0 0
T22 1045 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 159 0 0

SrcPulseCheck_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 19070296 107914 0 0
T1 40511 963 0 0
T2 323295 786 0 0
T3 461 101 0 0
T4 162 87 0 0
T8 0 729 0 0
T9 0 62 0 0
T10 0 583 0 0
T15 373 0 0 0
T16 361 0 0 0
T17 91 0 0 0
T18 461 0 0 0
T19 130 0 0 0
T22 156 0 0 0
T23 0 12 0 0
T24 0 26 0 0
T25 0 159 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%