Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	168943355	5608046	0	0
clk_enables_rd_A	168943355	42641	0	0
clk_hints_rd_A	168943355	37852	0	0
extclk_ctrl_rd_A	168943355	47282	0	0
extclk_ctrl_regwen_rd_A	168943355	35130	0	0
jitter_enable_rd_A	168943355	51356	0	0
jitter_regwen_rd_A	168943355	40132	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168943355	5608046	0	0
T1	217569	104371	0	0
T2	344632	122604	0	0
T3	214750	0	0	0
T8	0	69316	0	0
T11	0	97023	0	0
T13	0	238755	0	0
T14	0	114835	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T21	1134	0	0	0
T28	0	27175	0	0
T32	0	68342	0	0
T56	0	100452	0	0
T57	0	53539	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168943355	42641	0	0
T8	198041	0	0	0
T24	22425	0	0	0
T25	40651	0	0	0
T26	19180	0	0	0
T28	0	1087	0	0
T36	1700	1	0	0
T56	0	2068	0	0
T57	0	2092	0	0
T58	1515	0	0	0
T59	796	0	0	0
T63	0	1	0	0
T73	1310	0	0	0
T95	1813	0	0	0
T96	1344	0	0	0
T115	0	5	0	0
T116	0	2	0	0
T117	0	1854	0	0
T118	0	1	0	0
T119	0	2834	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168943355	37852	0	0
T8	198041	0	0	0
T24	22425	0	0	0
T25	40651	0	0	0
T26	19180	0	0	0
T28	0	888	0	0
T36	1700	2	0	0
T56	0	1864	0	0
T57	0	1972	0	0
T58	1515	0	0	0
T59	796	0	0	0
T73	1310	0	0	0
T95	1813	0	0	0
T96	1344	0	0	0
T116	0	6	0	0
T117	0	1706	0	0
T118	0	8	0	0
T119	0	2388	0	0
T120	0	6	0	0
T121	0	1509	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168943355	47282	0	0
T1	217569	0	0	0
T2	344632	0	0	0
T4	21691	0	0	0
T5	2659	80	0	0
T6	1049	0	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	0	0	0
T18	1515	0	0	0
T19	0	6	0	0
T22	1117	0	0	0
T26	0	53	0	0
T28	0	1197	0	0
T43	0	3	0	0
T56	0	2149	0	0
T62	0	101	0	0
T84	0	25	0	0
T122	0	18	0	0
T123	0	36	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168943355	35130	0	0
T8	198041	0	0	0
T9	148783	0	0	0
T26	19180	20	0	0
T27	65600	0	0	0
T28	0	947	0	0
T30	1255	0	0	0
T56	0	1857	0	0
T57	0	1777	0	0
T62	0	37	0	0
T73	1310	0	0	0
T84	0	3	0	0
T94	1829	0	0	0
T95	1813	0	0	0
T96	1344	0	0	0
T117	0	1579	0	0
T124	0	64	0	0
T125	0	42	0	0
T126	0	29	0	0
T127	1303	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168943355	51356	0	0
T8	198041	0	0	0
T24	22425	0	0	0
T25	40651	0	0	0
T26	19180	0	0	0
T28	0	1929	0	0
T36	1700	121	0	0
T56	0	2698	0	0
T57	0	2666	0	0
T58	1515	0	0	0
T59	796	0	0	0
T63	0	95	0	0
T73	1310	0	0	0
T95	1813	0	0	0
T96	1344	0	0	0
T115	0	73	0	0
T116	0	109	0	0
T117	0	2586	0	0
T120	0	118	0	0
T128	0	80	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168943355	40132	0	0
T28	933582	805	0	0
T29	35656	0	0	0
T56	320486	1948	0	0
T57	0	2055	0	0
T61	227396	0	0	0
T84	9438	0	0	0
T117	0	1812	0	0
T119	0	2589	0	0
T121	0	1542	0	0
T122	1816	0	0	0
T129	0	4811	0	0
T130	0	5346	0	0
T131	0	1378	0	0
T132	0	5900	0	0
T133	1570	0	0	0
T134	1253	0	0	0
T135	1164	0	0	0
T136	1109	0	0	0