Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T4
10CoveredT5,T1,T15
11CoveredT5,T1,T15

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 484410189 4420 0 0
g_div2.Div2Whole_A 484410189 5226 0 0
g_div4.Div4Stepped_A 241688596 4295 0 0
g_div4.Div4Whole_A 241688596 4899 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 484410189 4420 0 0
T1 196589 34 0 0
T2 678864 56 0 0
T4 83294 0 0 0
T5 10642 11 0 0
T6 2965 0 0 0
T8 0 25 0 0
T15 5127 7 0 0
T16 4963 0 0 0
T17 1137 0 0 0
T18 6322 10 0 0
T19 0 2 0 0
T20 0 1 0 0
T22 2095 0 0 0
T25 0 11 0 0
T73 0 8 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 484410189 5226 0 0
T1 196589 46 0 0
T2 678864 62 0 0
T4 83294 0 0 0
T5 10642 13 0 0
T6 2965 0 0 0
T8 0 30 0 0
T15 5127 8 0 0
T16 4963 0 0 0
T17 1137 0 0 0
T18 6322 8 0 0
T19 0 2 0 0
T20 0 1 0 0
T22 2095 0 0 0
T25 0 11 0 0
T73 0 8 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241688596 4295 0 0
T1 978027 33 0 0
T2 339075 55 0 0
T4 41601 0 0 0
T5 5828 11 0 0
T6 1429 0 0 0
T8 0 25 0 0
T15 2927 7 0 0
T16 2442 0 0 0
T17 543 0 0 0
T18 3669 9 0 0
T19 0 2 0 0
T20 0 1 0 0
T22 1015 0 0 0
T25 0 11 0 0
T73 0 8 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241688596 4899 0 0
T1 978027 34 0 0
T2 339075 62 0 0
T4 41601 0 0 0
T5 5828 13 0 0
T6 1429 0 0 0
T8 0 25 0 0
T15 2927 7 0 0
T16 2442 0 0 0
T17 543 0 0 0
T18 3669 7 0 0
T19 0 2 0 0
T20 0 1 0 0
T22 1015 0 0 0
T25 0 11 0 0
T73 0 7 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T4
10CoveredT5,T1,T15
11CoveredT5,T1,T15

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 484410189 4420 0 0
g_div2.Div2Whole_A 484410189 5226 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 484410189 4420 0 0
T1 196589 34 0 0
T2 678864 56 0 0
T4 83294 0 0 0
T5 10642 11 0 0
T6 2965 0 0 0
T8 0 25 0 0
T15 5127 7 0 0
T16 4963 0 0 0
T17 1137 0 0 0
T18 6322 10 0 0
T19 0 2 0 0
T20 0 1 0 0
T22 2095 0 0 0
T25 0 11 0 0
T73 0 8 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 484410189 5226 0 0
T1 196589 46 0 0
T2 678864 62 0 0
T4 83294 0 0 0
T5 10642 13 0 0
T6 2965 0 0 0
T8 0 30 0 0
T15 5127 8 0 0
T16 4963 0 0 0
T17 1137 0 0 0
T18 6322 8 0 0
T19 0 2 0 0
T20 0 1 0 0
T22 2095 0 0 0
T25 0 11 0 0
T73 0 8 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T4
10CoveredT5,T1,T15
11CoveredT5,T1,T15

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 241688596 4295 0 0
g_div4.Div4Whole_A 241688596 4899 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241688596 4295 0 0
T1 978027 33 0 0
T2 339075 55 0 0
T4 41601 0 0 0
T5 5828 11 0 0
T6 1429 0 0 0
T8 0 25 0 0
T15 2927 7 0 0
T16 2442 0 0 0
T17 543 0 0 0
T18 3669 9 0 0
T19 0 2 0 0
T20 0 1 0 0
T22 1015 0 0 0
T25 0 11 0 0
T73 0 8 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 241688596 4899 0 0
T1 978027 34 0 0
T2 339075 62 0 0
T4 41601 0 0 0
T5 5828 13 0 0
T6 1429 0 0 0
T8 0 25 0 0
T15 2927 7 0 0
T16 2442 0 0 0
T17 543 0 0 0
T18 3669 7 0 0
T19 0 2 0 0
T20 0 1 0 0
T22 1015 0 0 0
T25 0 11 0 0
T73 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%