SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T5,T1,T15 |
1 | 1 | Covered | T5,T1,T15 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 484410189 | 4420 | 0 | 0 |
g_div2.Div2Whole_A | 484410189 | 5226 | 0 | 0 |
g_div4.Div4Stepped_A | 241688596 | 4295 | 0 | 0 |
g_div4.Div4Whole_A | 241688596 | 4899 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 484410189 | 4420 | 0 | 0 |
T1 | 196589 | 34 | 0 | 0 |
T2 | 678864 | 56 | 0 | 0 |
T4 | 83294 | 0 | 0 | 0 |
T5 | 10642 | 11 | 0 | 0 |
T6 | 2965 | 0 | 0 | 0 |
T8 | 0 | 25 | 0 | 0 |
T15 | 5127 | 7 | 0 | 0 |
T16 | 4963 | 0 | 0 | 0 |
T17 | 1137 | 0 | 0 | 0 |
T18 | 6322 | 10 | 0 | 0 |
T19 | 0 | 2 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T22 | 2095 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T73 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 484410189 | 5226 | 0 | 0 |
T1 | 196589 | 46 | 0 | 0 |
T2 | 678864 | 62 | 0 | 0 |
T4 | 83294 | 0 | 0 | 0 |
T5 | 10642 | 13 | 0 | 0 |
T6 | 2965 | 0 | 0 | 0 |
T8 | 0 | 30 | 0 | 0 |
T15 | 5127 | 8 | 0 | 0 |
T16 | 4963 | 0 | 0 | 0 |
T17 | 1137 | 0 | 0 | 0 |
T18 | 6322 | 8 | 0 | 0 |
T19 | 0 | 2 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T22 | 2095 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T73 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 241688596 | 4295 | 0 | 0 |
T1 | 978027 | 33 | 0 | 0 |
T2 | 339075 | 55 | 0 | 0 |
T4 | 41601 | 0 | 0 | 0 |
T5 | 5828 | 11 | 0 | 0 |
T6 | 1429 | 0 | 0 | 0 |
T8 | 0 | 25 | 0 | 0 |
T15 | 2927 | 7 | 0 | 0 |
T16 | 2442 | 0 | 0 | 0 |
T17 | 543 | 0 | 0 | 0 |
T18 | 3669 | 9 | 0 | 0 |
T19 | 0 | 2 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T22 | 1015 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T73 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 241688596 | 4899 | 0 | 0 |
T1 | 978027 | 34 | 0 | 0 |
T2 | 339075 | 62 | 0 | 0 |
T4 | 41601 | 0 | 0 | 0 |
T5 | 5828 | 13 | 0 | 0 |
T6 | 1429 | 0 | 0 | 0 |
T8 | 0 | 25 | 0 | 0 |
T15 | 2927 | 7 | 0 | 0 |
T16 | 2442 | 0 | 0 | 0 |
T17 | 543 | 0 | 0 | 0 |
T18 | 3669 | 7 | 0 | 0 |
T19 | 0 | 2 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T22 | 1015 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T73 | 0 | 7 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T5,T1,T15 |
1 | 1 | Covered | T5,T1,T15 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 484410189 | 4420 | 0 | 0 |
g_div2.Div2Whole_A | 484410189 | 5226 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 484410189 | 4420 | 0 | 0 |
T1 | 196589 | 34 | 0 | 0 |
T2 | 678864 | 56 | 0 | 0 |
T4 | 83294 | 0 | 0 | 0 |
T5 | 10642 | 11 | 0 | 0 |
T6 | 2965 | 0 | 0 | 0 |
T8 | 0 | 25 | 0 | 0 |
T15 | 5127 | 7 | 0 | 0 |
T16 | 4963 | 0 | 0 | 0 |
T17 | 1137 | 0 | 0 | 0 |
T18 | 6322 | 10 | 0 | 0 |
T19 | 0 | 2 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T22 | 2095 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T73 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 484410189 | 5226 | 0 | 0 |
T1 | 196589 | 46 | 0 | 0 |
T2 | 678864 | 62 | 0 | 0 |
T4 | 83294 | 0 | 0 | 0 |
T5 | 10642 | 13 | 0 | 0 |
T6 | 2965 | 0 | 0 | 0 |
T8 | 0 | 30 | 0 | 0 |
T15 | 5127 | 8 | 0 | 0 |
T16 | 4963 | 0 | 0 | 0 |
T17 | 1137 | 0 | 0 | 0 |
T18 | 6322 | 8 | 0 | 0 |
T19 | 0 | 2 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T22 | 2095 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T73 | 0 | 8 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T5,T1,T15 |
1 | 1 | Covered | T5,T1,T15 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 241688596 | 4295 | 0 | 0 |
g_div4.Div4Whole_A | 241688596 | 4899 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 241688596 | 4295 | 0 | 0 |
T1 | 978027 | 33 | 0 | 0 |
T2 | 339075 | 55 | 0 | 0 |
T4 | 41601 | 0 | 0 | 0 |
T5 | 5828 | 11 | 0 | 0 |
T6 | 1429 | 0 | 0 | 0 |
T8 | 0 | 25 | 0 | 0 |
T15 | 2927 | 7 | 0 | 0 |
T16 | 2442 | 0 | 0 | 0 |
T17 | 543 | 0 | 0 | 0 |
T18 | 3669 | 9 | 0 | 0 |
T19 | 0 | 2 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T22 | 1015 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T73 | 0 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 241688596 | 4899 | 0 | 0 |
T1 | 978027 | 34 | 0 | 0 |
T2 | 339075 | 62 | 0 | 0 |
T4 | 41601 | 0 | 0 | 0 |
T5 | 5828 | 13 | 0 | 0 |
T6 | 1429 | 0 | 0 | 0 |
T8 | 0 | 25 | 0 | 0 |
T15 | 2927 | 7 | 0 | 0 |
T16 | 2442 | 0 | 0 | 0 |
T17 | 543 | 0 | 0 | 0 |
T18 | 3669 | 7 | 0 | 0 |
T19 | 0 | 2 | 0 | 0 |
T20 | 0 | 1 | 0 | 0 |
T22 | 1015 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T73 | 0 | 7 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |