Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	503809848	480	0	0
StatusRise_A	503809848	480	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503809848	480	0	0
T1	652707	0	0	0
T2	1033896	0	0	0
T3	644250	0	0	0
T15	4326	0	0	0
T16	3873	0	0	0
T17	3942	7	0	0
T18	4545	0	0	0
T19	2910	0	0	0
T20	3339	0	0	0
T22	3351	3	0	0
T34	0	7	0	0
T135	0	11	0	0
T137	0	14	0	0
T138	0	11	0	0
T139	0	18	0	0
T140	0	8	0	0
T141	0	8	0	0
T142	0	15	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503809848	480	0	0
T1	652707	0	0	0
T2	1033896	0	0	0
T3	644250	0	0	0
T15	4326	0	0	0
T16	3873	0	0	0
T17	3942	7	0	0
T18	4545	0	0	0
T19	2910	0	0	0
T20	3339	0	0	0
T22	3351	3	0	0
T34	0	7	0	0
T135	0	11	0	0
T137	0	14	0	0
T138	0	11	0	0
T139	0	18	0	0
T140	0	8	0	0
T141	0	8	0	0
T142	0	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167936616	155	0	0
StatusRise_A	167936616	155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	155	0	0
T1	217569	0	0	0
T2	344632	0	0	0
T3	214750	0	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	3	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T22	1117	1	0	0
T34	0	2	0	0
T135	0	3	0	0
T137	0	5	0	0
T138	0	3	0	0
T139	0	7	0	0
T140	0	2	0	0
T141	0	3	0	0
T142	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	155	0	0
T1	217569	0	0	0
T2	344632	0	0	0
T3	214750	0	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	3	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T22	1117	1	0	0
T34	0	2	0	0
T135	0	3	0	0
T137	0	5	0	0
T138	0	3	0	0
T139	0	7	0	0
T140	0	2	0	0
T141	0	3	0	0
T142	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167936616	164	0	0
StatusRise_A	167936616	164	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	164	0	0
T1	217569	0	0	0
T2	344632	0	0	0
T3	214750	0	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	2	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T22	1117	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0
T140	0	3	0	0
T141	0	2	0	0
T142	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	164	0	0
T1	217569	0	0	0
T2	344632	0	0	0
T3	214750	0	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	2	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T22	1117	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0
T140	0	3	0	0
T141	0	2	0	0
T142	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167936616	161	0	0
StatusRise_A	167936616	161	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	161	0	0
T1	217569	0	0	0
T2	344632	0	0	0
T3	214750	0	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	2	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T22	1117	1	0	0
T34	0	3	0	0
T135	0	4	0	0
T137	0	6	0	0
T138	0	4	0	0
T139	0	6	0	0
T140	0	3	0	0
T141	0	3	0	0
T142	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167936616	161	0	0
T1	217569	0	0	0
T2	344632	0	0	0
T3	214750	0	0	0
T15	1442	0	0	0
T16	1291	0	0	0
T17	1314	2	0	0
T18	1515	0	0	0
T19	970	0	0	0
T20	1113	0	0	0
T22	1117	1	0	0
T34	0	3	0	0
T135	0	4	0	0
T137	0	6	0	0
T138	0	4	0	0
T139	0	6	0	0
T140	0	3	0	0
T141	0	3	0	0
T142	0	5	0	0