Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47631	0	0
CgEnOn_A	2147483647	38256	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47631	0	0
T1	5818330	178	0	0
T2	7686440	270	0	0
T3	1261518	0	0	0
T4	405888	3	0	0
T5	24702	3	0	0
T6	15853	7	0	0
T15	59128	3	0	0
T16	55666	3	0	0
T17	12992	22	0	0
T18	73142	3	0	0
T19	16219	0	0	0
T20	12670	0	0	0
T21	0	3	0	0
T22	23552	12	0	0
T25	0	11	0	0
T28	0	10	0	0
T32	0	5	0	0
T34	0	10	0	0
T36	0	1	0	0
T58	0	1	0	0
T135	0	20	0	0
T137	0	15	0	0
T138	0	20	0	0
T139	0	25	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38256	0	0
T1	5818330	100	0	0
T2	7686440	189	0	0
T3	1744610	0	0	0
T4	224304	0	0	0
T6	9264	0	0	0
T8	0	75	0	0
T10	0	118	0	0
T15	59128	0	0	0
T16	55666	0	0	0
T17	12992	16	0	0
T18	73142	0	0	0
T19	20308	0	0	0
T20	17493	0	0	0
T22	23552	8	0	0
T25	0	3	0	0
T28	0	8	0	0
T32	0	4	0	0
T34	0	10	0	0
T36	0	3	0	0
T58	0	1	0	0
T59	0	23	0	0
T96	0	2	0	0
T135	0	20	0	0
T137	0	15	0	0
T138	0	20	0	0
T139	0	25	0	0
T140	0	3	0	0
T141	0	2	0	0
T142	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	241688221	177	0	0
CgEnOn_A	241688221	177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241688221	177	0	0
T1	978027	1	0	0
T2	339075	0	0	0
T3	107308	0	0	0
T15	2927	0	0	0
T16	2441	0	0	0
T17	543	2	0	0
T18	3668	0	0	0
T19	935	0	0	0
T20	1036	0	0	0
T22	1014	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241688221	177	0	0
T1	978027	1	0	0
T2	339075	0	0	0
T3	107308	0	0	0
T15	2927	0	0	0
T16	2441	0	0	0
T17	543	2	0	0
T18	3668	0	0	0
T19	935	0	0	0
T20	1036	0	0	0
T22	1014	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120843490	177	0	0
CgEnOn_A	120843490	177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843490	177	0	0
T1	489008	1	0	0
T2	169536	0	0	0
T3	53654	0	0	0
T15	1462	0	0	0
T16	1221	0	0	0
T17	271	2	0	0
T18	1833	0	0	0
T19	467	0	0	0
T20	517	0	0	0
T22	507	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843490	177	0	0
T1	489008	1	0	0
T2	169536	0	0	0
T3	53654	0	0	0
T15	1462	0	0	0
T16	1221	0	0	0
T17	271	2	0	0
T18	1833	0	0	0
T19	467	0	0	0
T20	517	0	0	0
T22	507	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120843490	177	0	0
CgEnOn_A	120843490	177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843490	177	0	0
T1	489008	1	0	0
T2	169536	0	0	0
T3	53654	0	0	0
T15	1462	0	0	0
T16	1221	0	0	0
T17	271	2	0	0
T18	1833	0	0	0
T19	467	0	0	0
T20	517	0	0	0
T22	507	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843490	177	0	0
T1	489008	1	0	0
T2	169536	0	0	0
T3	53654	0	0	0
T15	1462	0	0	0
T16	1221	0	0	0
T17	271	2	0	0
T18	1833	0	0	0
T19	467	0	0	0
T20	517	0	0	0
T22	507	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120843490	177	0	0
CgEnOn_A	120843490	177	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843490	177	0	0
T1	489008	1	0	0
T2	169536	0	0	0
T3	53654	0	0	0
T15	1462	0	0	0
T16	1221	0	0	0
T17	271	2	0	0
T18	1833	0	0	0
T19	467	0	0	0
T20	517	0	0	0
T22	507	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843490	177	0	0
T1	489008	1	0	0
T2	169536	0	0	0
T3	53654	0	0	0
T15	1462	0	0	0
T16	1221	0	0	0
T17	271	2	0	0
T18	1833	0	0	0
T19	467	0	0	0
T20	517	0	0	0
T22	507	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	484409743	177	0	0
CgEnOn_A	484409743	165	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484409743	177	0	0
T1	196589	1	0	0
T2	678864	0	0	0
T3	214750	0	0	0
T15	5127	0	0	0
T16	4962	0	0	0
T17	1137	2	0	0
T18	6321	0	0	0
T19	1791	0	0	0
T20	2180	0	0	0
T22	2094	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484409743	165	0	0
T1	196589	0	0	0
T2	678864	0	0	0
T3	214750	0	0	0
T15	5127	0	0	0
T16	4962	0	0	0
T17	1137	2	0	0
T18	6321	0	0	0
T19	1791	0	0	0
T20	2180	0	0	0
T22	2094	1	0	0
T34	0	2	0	0
T135	0	4	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	5	0	0
T140	0	3	0	0
T141	0	2	0	0
T142	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	515493652	158	0	0
CgEnOn_A	515493652	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	158	0	0
T1	217808	0	0	0
T2	714435	1	0	0
T3	223706	0	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T20	2271	0	0	0
T22	2203	1	0	0
T34	0	2	0	0
T135	0	3	0	0
T137	0	5	0	0
T138	0	3	0	0
T139	0	7	0	0
T140	0	2	0	0
T141	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	156	0	0
T1	217808	0	0	0
T2	714435	0	0	0
T3	223706	0	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T20	2271	0	0	0
T22	2203	1	0	0
T34	0	2	0	0
T135	0	3	0	0
T137	0	5	0	0
T138	0	3	0	0
T139	0	7	0	0
T140	0	2	0	0
T141	0	3	0	0
T142	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	515493652	158	0	0
CgEnOn_A	515493652	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	158	0	0
T1	217808	0	0	0
T2	714435	1	0	0
T3	223706	0	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T20	2271	0	0	0
T22	2203	1	0	0
T34	0	2	0	0
T135	0	3	0	0
T137	0	5	0	0
T138	0	3	0	0
T139	0	7	0	0
T140	0	2	0	0
T141	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	156	0	0
T1	217808	0	0	0
T2	714435	0	0	0
T3	223706	0	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T20	2271	0	0	0
T22	2203	1	0	0
T34	0	2	0	0
T135	0	3	0	0
T137	0	5	0	0
T138	0	3	0	0
T139	0	7	0	0
T140	0	2	0	0
T141	0	3	0	0
T142	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	247421867	163	0	0
CgEnOn_A	247421867	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247421867	163	0	0
T1	103109	0	0	0
T2	342904	0	0	0
T3	107380	0	0	0
T11	0	1	0	0
T15	2563	0	0	0
T16	2481	0	0	0
T17	605	2	0	0
T18	3161	0	0	0
T19	896	0	0	0
T20	1090	0	0	0
T22	1045	1	0	0
T34	0	3	0	0
T135	0	4	0	0
T137	0	6	0	0
T138	0	4	0	0
T139	0	6	0	0
T140	0	3	0	0
T141	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247421867	161	0	0
T1	103109	0	0	0
T2	342904	0	0	0
T3	107380	0	0	0
T15	2563	0	0	0
T16	2481	0	0	0
T17	605	2	0	0
T18	3161	0	0	0
T19	896	0	0	0
T20	1090	0	0	0
T22	1045	1	0	0
T34	0	3	0	0
T135	0	4	0	0
T137	0	6	0	0
T138	0	4	0	0
T139	0	6	0	0
T140	0	3	0	0
T141	0	3	0	0
T142	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T17,T34
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120843490	7715	0	0
CgEnOn_A	120843490	5384	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843490	7715	0	0
T1	489008	33	0	0
T2	169536	70	0	0
T4	20800	1	0	0
T5	2913	1	0	0
T6	714	1	0	0
T15	1462	1	0	0
T16	1221	1	0	0
T17	271	3	0	0
T18	1833	1	0	0
T22	507	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120843490	5384	0	0
T1	489008	28	0	0
T2	169536	60	0	0
T3	53654	0	0	0
T8	0	26	0	0
T10	0	55	0	0
T15	1462	0	0	0
T16	1221	0	0	0
T17	271	2	0	0
T18	1833	0	0	0
T19	467	0	0	0
T20	517	0	0	0
T22	507	1	0	0
T25	0	1	0	0
T36	0	1	0	0
T59	0	9	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T17,T34
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	241688221	7808	0	0
CgEnOn_A	241688221	5477	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241688221	7808	0	0
T1	978027	40	0	0
T2	339075	74	0	0
T4	41601	1	0	0
T5	5828	1	0	0
T6	1429	1	0	0
T15	2927	1	0	0
T16	2441	1	0	0
T17	543	3	0	0
T18	3668	1	0	0
T22	1014	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241688221	5477	0	0
T1	978027	35	0	0
T2	339075	64	0	0
T3	107308	0	0	0
T8	0	24	0	0
T10	0	63	0	0
T15	2927	0	0	0
T16	2441	0	0	0
T17	543	2	0	0
T18	3668	0	0	0
T19	935	0	0	0
T20	1036	0	0	0
T22	1014	1	0	0
T25	0	1	0	0
T36	0	1	0	0
T59	0	7	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T17,T34
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	484409743	7817	0	0
CgEnOn_A	484409743	5474	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484409743	7817	0	0
T1	196589	39	0	0
T2	678864	75	0	0
T4	83294	1	0	0
T5	10641	1	0	0
T6	2964	1	0	0
T15	5127	1	0	0
T16	4962	1	0	0
T17	1137	3	0	0
T18	6321	1	0	0
T22	2094	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484409743	5474	0	0
T1	196589	33	0	0
T2	678864	65	0	0
T3	214750	0	0	0
T8	0	25	0	0
T15	5127	0	0	0
T16	4962	0	0	0
T17	1137	2	0	0
T18	6321	0	0	0
T19	1791	0	0	0
T20	2180	0	0	0
T22	2094	1	0	0
T25	0	1	0	0
T36	0	1	0	0
T58	0	1	0	0
T59	0	7	0	0
T95	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T17,T34
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	247421867	7753	0	0
CgEnOn_A	247421867	5409	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247421867	7753	0	0
T1	103109	37	0	0
T2	342904	72	0	0
T4	35889	1	0	0
T5	5320	1	0	0
T6	1482	1	0	0
T15	2563	1	0	0
T16	2481	1	0	0
T17	605	3	0	0
T18	3161	1	0	0
T22	1045	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247421867	5409	0	0
T1	103109	31	0	0
T2	342904	62	0	0
T3	107380	0	0	0
T8	0	25	0	0
T10	0	54	0	0
T15	2563	0	0	0
T16	2481	0	0	0
T17	605	2	0	0
T18	3161	0	0	0
T19	896	0	0	0
T20	1090	0	0	0
T22	1045	1	0	0
T25	0	1	0	0
T36	0	1	0	0
T59	0	9	0	0
T96	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	515493652	3780	0	0
CgEnOn_A	515493652	3778	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	3780	0	0
T1	217808	61	0	0
T2	714435	51	0	0
T4	74768	0	0	0
T6	3088	4	0	0
T8	0	11	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T21	0	3	0	0
T22	2203	1	0	0
T25	0	11	0	0
T36	0	1	0	0
T58	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	3778	0	0
T1	217808	61	0	0
T2	714435	50	0	0
T4	74768	0	0	0
T6	3088	4	0	0
T8	0	11	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T21	0	3	0	0
T22	2203	1	0	0
T25	0	11	0	0
T36	0	1	0	0
T58	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	515493652	3809	0	0
CgEnOn_A	515493652	3807	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	3809	0	0
T1	217808	61	0	0
T2	714435	52	0	0
T4	74768	0	0	0
T6	3088	1	0	0
T8	0	16	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T21	0	2	0	0
T22	2203	1	0	0
T25	0	9	0	0
T36	0	1	0	0
T58	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	3807	0	0
T1	217808	61	0	0
T2	714435	51	0	0
T4	74768	0	0	0
T6	3088	1	0	0
T8	0	16	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T21	0	2	0	0
T22	2203	1	0	0
T25	0	9	0	0
T36	0	1	0	0
T58	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	515493652	3860	0	0
CgEnOn_A	515493652	3858	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	3860	0	0
T1	217808	59	0	0
T2	714435	57	0	0
T4	74768	0	0	0
T6	3088	2	0	0
T8	0	20	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T21	0	3	0	0
T22	2203	1	0	0
T25	0	12	0	0
T36	0	1	0	0
T58	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	3858	0	0
T1	217808	59	0	0
T2	714435	56	0	0
T4	74768	0	0	0
T6	3088	2	0	0
T8	0	20	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T21	0	3	0	0
T22	2203	1	0	0
T25	0	12	0	0
T36	0	1	0	0
T58	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T1,T17
1	0	Covered	T1,T2,T21
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	515493652	3725	0	0
CgEnOn_A	515493652	3723	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	3725	0	0
T1	217808	54	0	0
T2	714435	56	0	0
T3	223706	0	0	0
T8	0	18	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T20	2271	0	0	0
T21	0	3	0	0
T22	2203	1	0	0
T25	0	8	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	515493652	3723	0	0
T1	217808	54	0	0
T2	714435	55	0	0
T3	223706	0	0	0
T8	0	18	0	0
T15	5341	0	0	0
T16	5169	0	0	0
T17	1223	3	0	0
T18	6585	0	0	0
T19	1866	0	0	0
T20	2271	0	0	0
T21	0	3	0	0
T22	2203	1	0	0
T25	0	8	0	0
T36	0	1	0	0
T58	0	1	0	0
T95	0	1	0	0