Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T8 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
T28 |
28 |
28 |
0 |
0 |
T29 |
28 |
28 |
0 |
0 |
T30 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2008290 |
2005886 |
0 |
0 |
T5 |
934387 |
931433 |
0 |
0 |
T6 |
1706295 |
1703409 |
0 |
0 |
T7 |
78612 |
77013 |
0 |
0 |
T8 |
204854 |
203990 |
0 |
0 |
T26 |
371073 |
370111 |
0 |
0 |
T27 |
41559 |
36378 |
0 |
0 |
T28 |
35507 |
29337 |
0 |
0 |
T29 |
36119 |
31840 |
0 |
0 |
T30 |
103524 |
100127 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1033958280 |
1014592350 |
0 |
14490 |
T1 |
104784 |
104628 |
0 |
18 |
T5 |
100488 |
100104 |
0 |
18 |
T6 |
179358 |
179034 |
0 |
18 |
T7 |
7536 |
7350 |
0 |
18 |
T8 |
4788 |
4746 |
0 |
18 |
T26 |
22134 |
22050 |
0 |
18 |
T27 |
9528 |
8250 |
0 |
18 |
T28 |
8184 |
6648 |
0 |
18 |
T29 |
7992 |
6960 |
0 |
18 |
T30 |
11070 |
10638 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
756782 |
755733 |
0 |
21 |
T5 |
319954 |
318760 |
0 |
21 |
T6 |
589270 |
588096 |
0 |
21 |
T7 |
27441 |
26808 |
0 |
21 |
T8 |
80866 |
80425 |
0 |
21 |
T26 |
138108 |
137653 |
0 |
21 |
T27 |
11127 |
9635 |
0 |
21 |
T28 |
9493 |
7701 |
0 |
21 |
T29 |
9847 |
8580 |
0 |
21 |
T30 |
35270 |
33916 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
195592 |
0 |
0 |
T1 |
756782 |
4 |
0 |
0 |
T2 |
0 |
753 |
0 |
0 |
T5 |
319954 |
4 |
0 |
0 |
T6 |
589270 |
4 |
0 |
0 |
T7 |
27441 |
54 |
0 |
0 |
T8 |
80866 |
10 |
0 |
0 |
T10 |
0 |
517 |
0 |
0 |
T17 |
0 |
9 |
0 |
0 |
T24 |
0 |
2 |
0 |
0 |
T26 |
138108 |
241 |
0 |
0 |
T27 |
11127 |
14 |
0 |
0 |
T28 |
9493 |
24 |
0 |
0 |
T29 |
9847 |
30 |
0 |
0 |
T30 |
35270 |
194 |
0 |
0 |
T38 |
0 |
98 |
0 |
0 |
T76 |
0 |
30 |
0 |
0 |
T80 |
0 |
65 |
0 |
0 |
T117 |
0 |
12 |
0 |
0 |
T118 |
0 |
65 |
0 |
0 |
T120 |
0 |
23 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
1146724 |
1145486 |
0 |
0 |
T5 |
513945 |
512530 |
0 |
0 |
T6 |
937667 |
936240 |
0 |
0 |
T7 |
43635 |
42816 |
0 |
0 |
T8 |
119200 |
118780 |
0 |
0 |
T26 |
210831 |
210369 |
0 |
0 |
T27 |
20904 |
18454 |
0 |
0 |
T28 |
17830 |
14949 |
0 |
0 |
T29 |
18280 |
16261 |
0 |
0 |
T30 |
57184 |
55534 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
423910290 |
419262214 |
0 |
0 |
T1 |
139710 |
139520 |
0 |
0 |
T5 |
55442 |
55239 |
0 |
0 |
T6 |
79252 |
79049 |
0 |
0 |
T7 |
4825 |
4717 |
0 |
0 |
T8 |
15342 |
15262 |
0 |
0 |
T26 |
25302 |
25222 |
0 |
0 |
T27 |
1539 |
1336 |
0 |
0 |
T28 |
1293 |
1048 |
0 |
0 |
T29 |
1391 |
1215 |
0 |
0 |
T30 |
6112 |
5881 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
423910290 |
419255134 |
0 |
2415 |
T1 |
139710 |
139517 |
0 |
3 |
T5 |
55442 |
55236 |
0 |
3 |
T6 |
79252 |
79046 |
0 |
3 |
T7 |
4825 |
4714 |
0 |
3 |
T8 |
15342 |
15259 |
0 |
3 |
T26 |
25302 |
25219 |
0 |
3 |
T27 |
1539 |
1333 |
0 |
3 |
T28 |
1293 |
1045 |
0 |
3 |
T29 |
1391 |
1212 |
0 |
3 |
T30 |
6112 |
5878 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
423910290 |
27568 |
0 |
0 |
T1 |
139710 |
0 |
0 |
0 |
T2 |
0 |
323 |
0 |
0 |
T5 |
55442 |
0 |
0 |
0 |
T6 |
79252 |
0 |
0 |
0 |
T7 |
4825 |
16 |
0 |
0 |
T8 |
15342 |
0 |
0 |
0 |
T10 |
0 |
231 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T26 |
25302 |
0 |
0 |
0 |
T27 |
1539 |
0 |
0 |
0 |
T28 |
1293 |
0 |
0 |
0 |
T29 |
1391 |
0 |
0 |
0 |
T30 |
6112 |
72 |
0 |
0 |
T38 |
0 |
49 |
0 |
0 |
T76 |
0 |
9 |
0 |
0 |
T117 |
0 |
5 |
0 |
0 |
T118 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169098725 |
0 |
2415 |
T1 |
17464 |
17438 |
0 |
3 |
T5 |
16748 |
16684 |
0 |
3 |
T6 |
29893 |
29839 |
0 |
3 |
T7 |
1256 |
1225 |
0 |
3 |
T8 |
798 |
791 |
0 |
3 |
T26 |
3689 |
3675 |
0 |
3 |
T27 |
1588 |
1375 |
0 |
3 |
T28 |
1364 |
1108 |
0 |
3 |
T29 |
1332 |
1160 |
0 |
3 |
T30 |
1845 |
1773 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
17177 |
0 |
0 |
T1 |
17464 |
0 |
0 |
0 |
T2 |
0 |
200 |
0 |
0 |
T5 |
16748 |
0 |
0 |
0 |
T6 |
29893 |
0 |
0 |
0 |
T7 |
1256 |
3 |
0 |
0 |
T8 |
798 |
0 |
0 |
0 |
T10 |
0 |
126 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T26 |
3689 |
0 |
0 |
0 |
T27 |
1588 |
0 |
0 |
0 |
T28 |
1364 |
0 |
0 |
0 |
T29 |
1332 |
0 |
0 |
0 |
T30 |
1845 |
26 |
0 |
0 |
T38 |
0 |
31 |
0 |
0 |
T76 |
0 |
9 |
0 |
0 |
T80 |
0 |
65 |
0 |
0 |
T117 |
0 |
3 |
0 |
0 |
T120 |
0 |
23 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T30,T17 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T17 |
0 |
Covered |
T7,T8,T5 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169098725 |
0 |
2415 |
T1 |
17464 |
17438 |
0 |
3 |
T5 |
16748 |
16684 |
0 |
3 |
T6 |
29893 |
29839 |
0 |
3 |
T7 |
1256 |
1225 |
0 |
3 |
T8 |
798 |
791 |
0 |
3 |
T26 |
3689 |
3675 |
0 |
3 |
T27 |
1588 |
1375 |
0 |
3 |
T28 |
1364 |
1108 |
0 |
3 |
T29 |
1332 |
1160 |
0 |
3 |
T30 |
1845 |
1773 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
19277 |
0 |
0 |
T1 |
17464 |
0 |
0 |
0 |
T2 |
0 |
230 |
0 |
0 |
T5 |
16748 |
0 |
0 |
0 |
T6 |
29893 |
0 |
0 |
0 |
T7 |
1256 |
15 |
0 |
0 |
T8 |
798 |
0 |
0 |
0 |
T10 |
0 |
160 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T26 |
3689 |
0 |
0 |
0 |
T27 |
1588 |
0 |
0 |
0 |
T28 |
1364 |
0 |
0 |
0 |
T29 |
1332 |
0 |
0 |
0 |
T30 |
1845 |
34 |
0 |
0 |
T38 |
0 |
18 |
0 |
0 |
T76 |
0 |
12 |
0 |
0 |
T117 |
0 |
4 |
0 |
0 |
T118 |
0 |
35 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
451152255 |
0 |
0 |
T1 |
145536 |
145410 |
0 |
0 |
T5 |
57754 |
57671 |
0 |
0 |
T6 |
112558 |
112446 |
0 |
0 |
T7 |
5026 |
4943 |
0 |
0 |
T8 |
15982 |
15956 |
0 |
0 |
T26 |
26357 |
26331 |
0 |
0 |
T27 |
1603 |
1463 |
0 |
0 |
T28 |
1368 |
1227 |
0 |
0 |
T29 |
1448 |
1336 |
0 |
0 |
T30 |
6367 |
6255 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
451152255 |
0 |
0 |
T1 |
145536 |
145410 |
0 |
0 |
T5 |
57754 |
57671 |
0 |
0 |
T6 |
112558 |
112446 |
0 |
0 |
T7 |
5026 |
4943 |
0 |
0 |
T8 |
15982 |
15956 |
0 |
0 |
T26 |
26357 |
26331 |
0 |
0 |
T27 |
1603 |
1463 |
0 |
0 |
T28 |
1368 |
1227 |
0 |
0 |
T29 |
1448 |
1336 |
0 |
0 |
T30 |
6367 |
6255 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
423910290 |
421604231 |
0 |
0 |
T1 |
139710 |
139589 |
0 |
0 |
T5 |
55442 |
55363 |
0 |
0 |
T6 |
79252 |
79145 |
0 |
0 |
T7 |
4825 |
4745 |
0 |
0 |
T8 |
15342 |
15317 |
0 |
0 |
T26 |
25302 |
25277 |
0 |
0 |
T27 |
1539 |
1404 |
0 |
0 |
T28 |
1293 |
1158 |
0 |
0 |
T29 |
1391 |
1283 |
0 |
0 |
T30 |
6112 |
6005 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
423910290 |
421604231 |
0 |
0 |
T1 |
139710 |
139589 |
0 |
0 |
T5 |
55442 |
55363 |
0 |
0 |
T6 |
79252 |
79145 |
0 |
0 |
T7 |
4825 |
4745 |
0 |
0 |
T8 |
15342 |
15317 |
0 |
0 |
T26 |
25302 |
25277 |
0 |
0 |
T27 |
1539 |
1404 |
0 |
0 |
T28 |
1293 |
1158 |
0 |
0 |
T29 |
1391 |
1283 |
0 |
0 |
T30 |
6112 |
6005 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
211070018 |
211070018 |
0 |
0 |
T1 |
69795 |
69795 |
0 |
0 |
T5 |
27682 |
27682 |
0 |
0 |
T6 |
39573 |
39573 |
0 |
0 |
T7 |
2488 |
2488 |
0 |
0 |
T8 |
7659 |
7659 |
0 |
0 |
T26 |
12639 |
12639 |
0 |
0 |
T27 |
702 |
702 |
0 |
0 |
T28 |
579 |
579 |
0 |
0 |
T29 |
642 |
642 |
0 |
0 |
T30 |
3408 |
3408 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
211070018 |
211070018 |
0 |
0 |
T1 |
69795 |
69795 |
0 |
0 |
T5 |
27682 |
27682 |
0 |
0 |
T6 |
39573 |
39573 |
0 |
0 |
T7 |
2488 |
2488 |
0 |
0 |
T8 |
7659 |
7659 |
0 |
0 |
T26 |
12639 |
12639 |
0 |
0 |
T27 |
702 |
702 |
0 |
0 |
T28 |
579 |
579 |
0 |
0 |
T29 |
642 |
642 |
0 |
0 |
T30 |
3408 |
3408 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105534361 |
105534361 |
0 |
0 |
T1 |
34897 |
34897 |
0 |
0 |
T5 |
13841 |
13841 |
0 |
0 |
T6 |
19786 |
19786 |
0 |
0 |
T7 |
1243 |
1243 |
0 |
0 |
T8 |
3829 |
3829 |
0 |
0 |
T26 |
6319 |
6319 |
0 |
0 |
T27 |
351 |
351 |
0 |
0 |
T28 |
290 |
290 |
0 |
0 |
T29 |
321 |
321 |
0 |
0 |
T30 |
1704 |
1704 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
105534361 |
105534361 |
0 |
0 |
T1 |
34897 |
34897 |
0 |
0 |
T5 |
13841 |
13841 |
0 |
0 |
T6 |
19786 |
19786 |
0 |
0 |
T7 |
1243 |
1243 |
0 |
0 |
T8 |
3829 |
3829 |
0 |
0 |
T26 |
6319 |
6319 |
0 |
0 |
T27 |
351 |
351 |
0 |
0 |
T28 |
290 |
290 |
0 |
0 |
T29 |
321 |
321 |
0 |
0 |
T30 |
1704 |
1704 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217552577 |
216388016 |
0 |
0 |
T1 |
69858 |
69797 |
0 |
0 |
T5 |
27722 |
27683 |
0 |
0 |
T6 |
56908 |
56854 |
0 |
0 |
T7 |
2413 |
2373 |
0 |
0 |
T8 |
7672 |
7659 |
0 |
0 |
T26 |
12652 |
12639 |
0 |
0 |
T27 |
769 |
702 |
0 |
0 |
T28 |
644 |
577 |
0 |
0 |
T29 |
694 |
641 |
0 |
0 |
T30 |
3055 |
3002 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
217552577 |
216388016 |
0 |
0 |
T1 |
69858 |
69797 |
0 |
0 |
T5 |
27722 |
27683 |
0 |
0 |
T6 |
56908 |
56854 |
0 |
0 |
T7 |
2413 |
2373 |
0 |
0 |
T8 |
7672 |
7659 |
0 |
0 |
T26 |
12652 |
12639 |
0 |
0 |
T27 |
769 |
702 |
0 |
0 |
T28 |
644 |
577 |
0 |
0 |
T29 |
694 |
641 |
0 |
0 |
T30 |
3055 |
3002 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169098725 |
0 |
2415 |
T1 |
17464 |
17438 |
0 |
3 |
T5 |
16748 |
16684 |
0 |
3 |
T6 |
29893 |
29839 |
0 |
3 |
T7 |
1256 |
1225 |
0 |
3 |
T8 |
798 |
791 |
0 |
3 |
T26 |
3689 |
3675 |
0 |
3 |
T27 |
1588 |
1375 |
0 |
3 |
T28 |
1364 |
1108 |
0 |
3 |
T29 |
1332 |
1160 |
0 |
3 |
T30 |
1845 |
1773 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169098725 |
0 |
2415 |
T1 |
17464 |
17438 |
0 |
3 |
T5 |
16748 |
16684 |
0 |
3 |
T6 |
29893 |
29839 |
0 |
3 |
T7 |
1256 |
1225 |
0 |
3 |
T8 |
798 |
791 |
0 |
3 |
T26 |
3689 |
3675 |
0 |
3 |
T27 |
1588 |
1375 |
0 |
3 |
T28 |
1364 |
1108 |
0 |
3 |
T29 |
1332 |
1160 |
0 |
3 |
T30 |
1845 |
1773 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169098725 |
0 |
2415 |
T1 |
17464 |
17438 |
0 |
3 |
T5 |
16748 |
16684 |
0 |
3 |
T6 |
29893 |
29839 |
0 |
3 |
T7 |
1256 |
1225 |
0 |
3 |
T8 |
798 |
791 |
0 |
3 |
T26 |
3689 |
3675 |
0 |
3 |
T27 |
1588 |
1375 |
0 |
3 |
T28 |
1364 |
1108 |
0 |
3 |
T29 |
1332 |
1160 |
0 |
3 |
T30 |
1845 |
1773 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169098725 |
0 |
2415 |
T1 |
17464 |
17438 |
0 |
3 |
T5 |
16748 |
16684 |
0 |
3 |
T6 |
29893 |
29839 |
0 |
3 |
T7 |
1256 |
1225 |
0 |
3 |
T8 |
798 |
791 |
0 |
3 |
T26 |
3689 |
3675 |
0 |
3 |
T27 |
1588 |
1375 |
0 |
3 |
T28 |
1364 |
1108 |
0 |
3 |
T29 |
1332 |
1160 |
0 |
3 |
T30 |
1845 |
1773 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169098725 |
0 |
2415 |
T1 |
17464 |
17438 |
0 |
3 |
T5 |
16748 |
16684 |
0 |
3 |
T6 |
29893 |
29839 |
0 |
3 |
T7 |
1256 |
1225 |
0 |
3 |
T8 |
798 |
791 |
0 |
3 |
T26 |
3689 |
3675 |
0 |
3 |
T27 |
1588 |
1375 |
0 |
3 |
T28 |
1364 |
1108 |
0 |
3 |
T29 |
1332 |
1160 |
0 |
3 |
T30 |
1845 |
1773 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169098725 |
0 |
2415 |
T1 |
17464 |
17438 |
0 |
3 |
T5 |
16748 |
16684 |
0 |
3 |
T6 |
29893 |
29839 |
0 |
3 |
T7 |
1256 |
1225 |
0 |
3 |
T8 |
798 |
791 |
0 |
3 |
T26 |
3689 |
3675 |
0 |
3 |
T27 |
1588 |
1375 |
0 |
3 |
T28 |
1364 |
1108 |
0 |
3 |
T29 |
1332 |
1160 |
0 |
3 |
T30 |
1845 |
1773 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
172326380 |
169105949 |
0 |
0 |
T1 |
17464 |
17441 |
0 |
0 |
T5 |
16748 |
16687 |
0 |
0 |
T6 |
29893 |
29842 |
0 |
0 |
T7 |
1256 |
1228 |
0 |
0 |
T8 |
798 |
794 |
0 |
0 |
T26 |
3689 |
3678 |
0 |
0 |
T27 |
1588 |
1378 |
0 |
0 |
T28 |
1364 |
1111 |
0 |
0 |
T29 |
1332 |
1163 |
0 |
0 |
T30 |
1845 |
1776 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448675042 |
0 |
2415 |
T1 |
145536 |
145335 |
0 |
3 |
T5 |
57754 |
57539 |
0 |
3 |
T6 |
112558 |
112343 |
0 |
3 |
T7 |
5026 |
4911 |
0 |
3 |
T8 |
15982 |
15896 |
0 |
3 |
T26 |
26357 |
26271 |
0 |
3 |
T27 |
1603 |
1388 |
0 |
3 |
T28 |
1368 |
1110 |
0 |
3 |
T29 |
1448 |
1262 |
0 |
3 |
T30 |
6367 |
6123 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
32921 |
0 |
0 |
T1 |
145536 |
1 |
0 |
0 |
T5 |
57754 |
1 |
0 |
0 |
T6 |
112558 |
1 |
0 |
0 |
T7 |
5026 |
5 |
0 |
0 |
T8 |
15982 |
3 |
0 |
0 |
T26 |
26357 |
64 |
0 |
0 |
T27 |
1603 |
3 |
0 |
0 |
T28 |
1368 |
5 |
0 |
0 |
T29 |
1448 |
8 |
0 |
0 |
T30 |
6367 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448675042 |
0 |
2415 |
T1 |
145536 |
145335 |
0 |
3 |
T5 |
57754 |
57539 |
0 |
3 |
T6 |
112558 |
112343 |
0 |
3 |
T7 |
5026 |
4911 |
0 |
3 |
T8 |
15982 |
15896 |
0 |
3 |
T26 |
26357 |
26271 |
0 |
3 |
T27 |
1603 |
1388 |
0 |
3 |
T28 |
1368 |
1110 |
0 |
3 |
T29 |
1448 |
1262 |
0 |
3 |
T30 |
6367 |
6123 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
32672 |
0 |
0 |
T1 |
145536 |
1 |
0 |
0 |
T5 |
57754 |
1 |
0 |
0 |
T6 |
112558 |
1 |
0 |
0 |
T7 |
5026 |
5 |
0 |
0 |
T8 |
15982 |
3 |
0 |
0 |
T26 |
26357 |
58 |
0 |
0 |
T27 |
1603 |
1 |
0 |
0 |
T28 |
1368 |
9 |
0 |
0 |
T29 |
1448 |
6 |
0 |
0 |
T30 |
6367 |
23 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448675042 |
0 |
2415 |
T1 |
145536 |
145335 |
0 |
3 |
T5 |
57754 |
57539 |
0 |
3 |
T6 |
112558 |
112343 |
0 |
3 |
T7 |
5026 |
4911 |
0 |
3 |
T8 |
15982 |
15896 |
0 |
3 |
T26 |
26357 |
26271 |
0 |
3 |
T27 |
1603 |
1388 |
0 |
3 |
T28 |
1368 |
1110 |
0 |
3 |
T29 |
1448 |
1262 |
0 |
3 |
T30 |
6367 |
6123 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
33174 |
0 |
0 |
T1 |
145536 |
1 |
0 |
0 |
T5 |
57754 |
1 |
0 |
0 |
T6 |
112558 |
1 |
0 |
0 |
T7 |
5026 |
5 |
0 |
0 |
T8 |
15982 |
3 |
0 |
0 |
T26 |
26357 |
62 |
0 |
0 |
T27 |
1603 |
5 |
0 |
0 |
T28 |
1368 |
5 |
0 |
0 |
T29 |
1448 |
6 |
0 |
0 |
T30 |
6367 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T5 |
1 | Covered | T7,T8,T5 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T5 |
0 |
Covered |
T7,T8,T5 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448675042 |
0 |
2415 |
T1 |
145536 |
145335 |
0 |
3 |
T5 |
57754 |
57539 |
0 |
3 |
T6 |
112558 |
112343 |
0 |
3 |
T7 |
5026 |
4911 |
0 |
3 |
T8 |
15982 |
15896 |
0 |
3 |
T26 |
26357 |
26271 |
0 |
3 |
T27 |
1603 |
1388 |
0 |
3 |
T28 |
1368 |
1110 |
0 |
3 |
T29 |
1448 |
1262 |
0 |
3 |
T30 |
6367 |
6123 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
32803 |
0 |
0 |
T1 |
145536 |
1 |
0 |
0 |
T5 |
57754 |
1 |
0 |
0 |
T6 |
112558 |
1 |
0 |
0 |
T7 |
5026 |
5 |
0 |
0 |
T8 |
15982 |
1 |
0 |
0 |
T26 |
26357 |
57 |
0 |
0 |
T27 |
1603 |
5 |
0 |
0 |
T28 |
1368 |
5 |
0 |
0 |
T29 |
1448 |
10 |
0 |
0 |
T30 |
6367 |
15 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
453594436 |
448682182 |
0 |
0 |
T1 |
145536 |
145338 |
0 |
0 |
T5 |
57754 |
57542 |
0 |
0 |
T6 |
112558 |
112346 |
0 |
0 |
T7 |
5026 |
4914 |
0 |
0 |
T8 |
15982 |
15899 |
0 |
0 |
T26 |
26357 |
26274 |
0 |
0 |
T27 |
1603 |
1391 |
0 |
0 |
T28 |
1368 |
1113 |
0 |
0 |
T29 |
1448 |
1265 |
0 |
0 |
T30 |
6367 |
6126 |
0 |
0 |