Unified Coverage Report :: Module :: clkmgr_meas_chk

Module : clkmgr_meas_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas	94.44	100.00	83.33			100.00
tb.dut.u_io_div2_meas	94.44	100.00	83.33			100.00
tb.dut.u_io_div4_meas	94.44	100.00	83.33			100.00
tb.dut.u_main_meas	94.44	100.00	83.33			100.00
tb.dut.u_usb_meas	94.44	100.00	83.33			100.00

---

Module Instance : tb.dut.u_io_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_io_div2_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_io_div4_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_main_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_usb_meas

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.78	100.00	95.56		100.00	100.00	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_calib_rdy_sync	100.00	100.00				100.00	100.00
u_err_sync	93.75	100.00	75.00			100.00	100.00
u_meas	94.29	100.00	100.00		100.00	100.00	71.43
u_timeout_err_sync	100.00	100.00	100.00			100.00

Line Coverage for Module : clkmgr_meas_chk

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
81	1	1
83	1	1
84	1	1
			MISSING_ELSE
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
			MISSING_ELSE

---

Cond Coverage for Module : clkmgr_meas_chk

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T3,T10
1	0	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

---

Branch Coverage for Module : clkmgr_meas_chk

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	93	if ((!rst_src_ni))
-2-:	95	if ((src_fast_err || src_slow_err))
-3-:	97	if ((src_err_req && src_err_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T7,T8,T5

Line Coverage for Instance : tb.dut.u_io_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
81	1	1
83	1	1
84	1	1
			MISSING_ELSE
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T10,T11
1	0	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

---

Branch Coverage for Instance : tb.dut.u_io_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	93	if ((!rst_src_ni))
-2-:	95	if ((src_fast_err || src_slow_err))
-3-:	97	if ((src_err_req && src_err_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T7,T8,T5

Line Coverage for Instance : tb.dut.u_io_div2_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
81	1	1
83	1	1
84	1	1
			MISSING_ELSE
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	93	if ((!rst_src_ni))
-2-:	95	if ((src_fast_err || src_slow_err))
-3-:	97	if ((src_err_req && src_err_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T5

Line Coverage for Instance : tb.dut.u_io_div4_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
81	1	1
83	1	1
84	1	1
			MISSING_ELSE
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T3,T10
1	0	Covered	T5,T1,T2

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	93	if ((!rst_src_ni))
-2-:	95	if ((src_fast_err || src_slow_err))
-3-:	97	if ((src_err_req && src_err_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T2
0	0	1	Covered	T5,T1,T2
0	0	0	Covered	T7,T8,T5

Line Coverage for Instance : tb.dut.u_main_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
81	1	1
83	1	1
84	1	1
			MISSING_ELSE
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_main_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T11,T12
1	0	Covered	T5,T2,T3

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T2,T3
1	1	Covered	T5,T2,T3

---

Branch Coverage for Instance : tb.dut.u_main_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	93	if ((!rst_src_ni))
-2-:	95	if ((src_fast_err || src_slow_err))
-3-:	97	if ((src_err_req && src_err_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T2,T3
0	0	1	Covered	T5,T2,T3
0	0	0	Covered	T7,T8,T5

Line Coverage for Instance : tb.dut.u_usb_meas

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	76	5	5	100.00
ALWAYS	93	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
81	1	1
83	1	1
84	1	1
			MISSING_ELSE
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
98	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_usb_meas

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       95
 EXPRESSION (src_fast_err || src_slow_err)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T2,T10,T13
1	0	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (src_err_req && src_err_ack)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_usb_meas

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	81	2	2	100.00
IF	93	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_meas_chk.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	93	if ((!rst_src_ni))
-2-:	95	if ((src_fast_err || src_slow_err))
-3-:	97	if ((src_err_req && src_err_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T7,T8,T5