Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_io_meas.u_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 100.00 100.00 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.29 100.00 100.00 100.00 100.00 71.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk 87.50 100.00 100.00 100.00 50.00
u_ref_meas_en_sync 100.00 100.00 100.00
u_sync_ref 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 100.00 100.00 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.29 100.00 100.00 100.00 100.00 71.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk 87.50 100.00 100.00 100.00 50.00
u_ref_meas_en_sync 100.00 100.00 100.00
u_sync_ref 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 100.00 100.00 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.29 100.00 100.00 100.00 100.00 71.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk 87.50 100.00 100.00 100.00 50.00
u_ref_meas_en_sync 100.00 100.00 100.00
u_sync_ref 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 100.00 100.00 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.29 100.00 100.00 100.00 100.00 71.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk 87.50 100.00 100.00 100.00 50.00
u_ref_meas_en_sync 100.00 100.00 100.00
u_sync_ref 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_meas

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 100.00 100.00 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.29 100.00 100.00 100.00 100.00 71.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
ack_sync 100.00 100.00 100.00
gen_clk_timeout_chk.u_timeout_ref_to_clk 87.50 100.00 100.00 100.00 50.00
u_ref_meas_en_sync 100.00 100.00 100.00
u_sync_ref 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_clock_meas
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS8833100.00
ALWAYS1001212100.00
CONT_ASSIGN16311100.00
ALWAYS1831313100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
89 1 1
91 1 1
100 1 1
101 1 1
103 1 1
106 1 1
107 1 1
MISSING_ELSE
112 1 1
113 1 1
MISSING_ELSE
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
MISSING_ELSE
163 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
195 1 1
MISSING_ELSE
199 1 1
200 1 1
201 1 1


Cond Coverage for Module : prim_clock_meas
TotalCoveredPercent
Conditions1515100.00
Logical1515100.00
Non-Logical00
Event00

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT7,T8,T5
11CoveredT5,T6,T1

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT5,T6,T1
11CoveredT5,T6,T1

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT5,T6,T1
11CoveredT5,T1,T2

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---
-1--2-StatusTests
00CoveredT7,T8,T5
01CoveredT5,T1,T2
10CoveredT5,T1,T2

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------
-1--2-StatusTests
01CoveredT7,T8,T5
10CoveredT5,T6,T1
11CoveredT2,T3,T10

FSM Coverage for Module : prim_clock_meas
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisable 126 Covered T7,T8,T5
StDisabling 120 Covered T5,T6,T1
StEnable 113 Covered T5,T6,T1
StEnabling 107 Covered T5,T6,T1


transitionsLine No.CoveredTests
StDisable->StEnabling 107 Covered T5,T6,T1
StDisabling->StDisable 126 Covered T5,T6,T1
StEnable->StDisabling 120 Covered T5,T6,T1
StEnabling->StEnable 113 Covered T5,T6,T1



Branch Coverage for Module : prim_clock_meas
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 88 2 2 100.00
CASE 103 8 8 100.00
IF 183 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T7,T8,T5
0 Covered T7,T8,T5


LineNo. Expression -1-: 103 case (state_q) -2-: 106 if (en_i) -3-: 112 if (en_ref_sync) -4-: 119 if ((!en_i)) -5-: 125 if ((!en_ref_sync))

Branches:
-1--2--3--4--5-StatusTests
StDisable 1 - - - Covered T5,T6,T1
StDisable 0 - - - Covered T5,T6,T1
StEnabling - 1 - - Covered T5,T6,T1
StEnabling - 0 - - Covered T5,T6,T1
StEnable - - 1 - Covered T5,T6,T1
StEnable - - 0 - Covered T5,T6,T1
StDisabling - - - 1 Covered T5,T6,T1
StDisabling - - - 0 Covered T5,T6,T1


LineNo. Expression -1-: 183 if ((!rst_ni)) -2-: 186 if (((!cnt_en) && (|cnt))) -3-: 189 if (valid_o) -4-: 192 if (cnt_ovfl) -5-: 194 if (cnt_en)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T7,T8,T5
0 1 - - - Covered T5,T6,T1
0 0 1 - - Covered T5,T6,T1
0 0 0 1 - Covered T5,T1,T2
0 0 0 0 1 Covered T5,T6,T1
0 0 0 0 0 Covered T7,T8,T5


Assert Coverage for Module : prim_clock_meas
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 2 66.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 2 66.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MaxWidth_A 1411661682 0 0 0
RefCntVal_A 4025 4025 0 0
gen_timeout_assert.ClkRatios_A 4025 4025 0 0


MaxWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1411661682 0 0 0

RefCntVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4025 4025 0 0
T1 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T7 5 5 0 0
T8 5 5 0 0
T26 5 5 0 0
T27 5 5 0 0
T28 5 5 0 0
T29 5 5 0 0
T30 5 5 0 0

gen_timeout_assert.ClkRatios_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4025 4025 0 0
T1 5 5 0 0
T5 5 5 0 0
T6 5 5 0 0
T7 5 5 0 0
T8 5 5 0 0
T26 5 5 0 0
T27 5 5 0 0
T28 5 5 0 0
T29 5 5 0 0
T30 5 5 0 0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS8833100.00
ALWAYS1001212100.00
CONT_ASSIGN16311100.00
ALWAYS1831313100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
89 1 1
91 1 1
100 1 1
101 1 1
103 1 1
106 1 1
107 1 1
MISSING_ELSE
112 1 1
113 1 1
MISSING_ELSE
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
MISSING_ELSE
163 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
195 1 1
MISSING_ELSE
199 1 1
200 1 1
201 1 1


Cond Coverage for Instance : tb.dut.u_io_meas.u_meas
TotalCoveredPercent
Conditions1515100.00
Logical1515100.00
Non-Logical00
Event00

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT7,T8,T5
11CoveredT5,T6,T1

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT5,T6,T1
11CoveredT5,T6,T1

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT5,T6,T1
11CoveredT5,T1,T2

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---
-1--2-StatusTests
00CoveredT7,T8,T5
01CoveredT5,T2,T3
10CoveredT5,T1,T2

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------
-1--2-StatusTests
01CoveredT7,T8,T5
10CoveredT5,T6,T1
11CoveredT2,T10,T11

FSM Coverage for Instance : tb.dut.u_io_meas.u_meas
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisable 126 Covered T7,T8,T5
StDisabling 120 Covered T5,T6,T1
StEnable 113 Covered T5,T6,T1
StEnabling 107 Covered T5,T6,T1


transitionsLine No.CoveredTests
StDisable->StEnabling 107 Covered T5,T6,T1
StDisabling->StDisable 126 Covered T5,T6,T1
StEnable->StDisabling 120 Covered T5,T6,T1
StEnabling->StEnable 113 Covered T5,T6,T1



Branch Coverage for Instance : tb.dut.u_io_meas.u_meas
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 88 2 2 100.00
CASE 103 8 8 100.00
IF 183 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T7,T8,T5
0 Covered T7,T8,T5


LineNo. Expression -1-: 103 case (state_q) -2-: 106 if (en_i) -3-: 112 if (en_ref_sync) -4-: 119 if ((!en_i)) -5-: 125 if ((!en_ref_sync))

Branches:
-1--2--3--4--5-StatusTests
StDisable 1 - - - Covered T5,T6,T1
StDisable 0 - - - Covered T5,T6,T1
StEnabling - 1 - - Covered T5,T6,T1
StEnabling - 0 - - Covered T5,T6,T1
StEnable - - 1 - Covered T5,T6,T1
StEnable - - 0 - Covered T5,T6,T1
StDisabling - - - 1 Covered T5,T6,T1
StDisabling - - - 0 Covered T5,T6,T1


LineNo. Expression -1-: 183 if ((!rst_ni)) -2-: 186 if (((!cnt_en) && (|cnt))) -3-: 189 if (valid_o) -4-: 192 if (cnt_ovfl) -5-: 194 if (cnt_en)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T7,T8,T5
0 1 - - - Covered T5,T6,T1
0 0 1 - - Covered T5,T6,T1
0 0 0 1 - Covered T5,T2,T3
0 0 0 0 1 Covered T5,T6,T1
0 0 0 0 0 Covered T7,T8,T5


Assert Coverage for Instance : tb.dut.u_io_meas.u_meas
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 2 66.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 2 66.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MaxWidth_A 423910290 0 0 0
RefCntVal_A 805 805 0 0
gen_timeout_assert.ClkRatios_A 805 805 0 0


MaxWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 423910290 0 0 0

RefCntVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

gen_timeout_assert.ClkRatios_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS8833100.00
ALWAYS1001212100.00
CONT_ASSIGN16311100.00
ALWAYS1831313100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
89 1 1
91 1 1
100 1 1
101 1 1
103 1 1
106 1 1
107 1 1
MISSING_ELSE
112 1 1
113 1 1
MISSING_ELSE
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
MISSING_ELSE
163 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
195 1 1
MISSING_ELSE
199 1 1
200 1 1
201 1 1


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas
TotalCoveredPercent
Conditions1515100.00
Logical1515100.00
Non-Logical00
Event00

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT7,T8,T5
11CoveredT5,T6,T1

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT5,T6,T1
11CoveredT5,T6,T1

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T1
11CoveredT1,T2,T3

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---
-1--2-StatusTests
00CoveredT7,T8,T5
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------
-1--2-StatusTests
01CoveredT7,T8,T5
10CoveredT5,T6,T1
11CoveredT2,T10,T12

FSM Coverage for Instance : tb.dut.u_io_div2_meas.u_meas
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisable 126 Covered T7,T8,T5
StDisabling 120 Covered T5,T6,T1
StEnable 113 Covered T5,T6,T1
StEnabling 107 Covered T5,T6,T1


transitionsLine No.CoveredTests
StDisable->StEnabling 107 Covered T5,T6,T1
StDisabling->StDisable 126 Covered T5,T6,T1
StEnable->StDisabling 120 Covered T5,T6,T1
StEnabling->StEnable 113 Covered T5,T6,T1



Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 88 2 2 100.00
CASE 103 8 8 100.00
IF 183 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T7,T8,T5
0 Covered T7,T8,T5


LineNo. Expression -1-: 103 case (state_q) -2-: 106 if (en_i) -3-: 112 if (en_ref_sync) -4-: 119 if ((!en_i)) -5-: 125 if ((!en_ref_sync))

Branches:
-1--2--3--4--5-StatusTests
StDisable 1 - - - Covered T5,T6,T1
StDisable 0 - - - Covered T5,T6,T1
StEnabling - 1 - - Covered T5,T6,T1
StEnabling - 0 - - Covered T5,T6,T1
StEnable - - 1 - Covered T5,T6,T1
StEnable - - 0 - Covered T5,T6,T1
StDisabling - - - 1 Covered T5,T6,T1
StDisabling - - - 0 Covered T5,T6,T1


LineNo. Expression -1-: 183 if ((!rst_ni)) -2-: 186 if (((!cnt_en) && (|cnt))) -3-: 189 if (valid_o) -4-: 192 if (cnt_ovfl) -5-: 194 if (cnt_en)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T7,T8,T5
0 1 - - - Covered T5,T6,T1
0 0 1 - - Covered T5,T6,T1
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T5,T6,T1
0 0 0 0 0 Covered T7,T8,T5


Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 2 66.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 2 66.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MaxWidth_A 211070018 0 0 0
RefCntVal_A 805 805 0 0
gen_timeout_assert.ClkRatios_A 805 805 0 0


MaxWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 211070018 0 0 0

RefCntVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

gen_timeout_assert.ClkRatios_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS8833100.00
ALWAYS1001212100.00
CONT_ASSIGN16311100.00
ALWAYS1831313100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
89 1 1
91 1 1
100 1 1
101 1 1
103 1 1
106 1 1
107 1 1
MISSING_ELSE
112 1 1
113 1 1
MISSING_ELSE
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
MISSING_ELSE
163 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
195 1 1
MISSING_ELSE
199 1 1
200 1 1
201 1 1


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas
TotalCoveredPercent
Conditions1515100.00
Logical1515100.00
Non-Logical00
Event00

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT7,T8,T5
11CoveredT5,T6,T1

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT5,T6,T1
11CoveredT5,T6,T1

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------
-1--2-StatusTests
01CoveredT5,T1,T2
10CoveredT5,T6,T1
11CoveredT5,T1,T2

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---
-1--2-StatusTests
00CoveredT7,T8,T5
01CoveredT5,T1,T2
10CoveredT5,T1,T2

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------
-1--2-StatusTests
01CoveredT7,T8,T5
10CoveredT5,T6,T1
11CoveredT2,T3,T10

FSM Coverage for Instance : tb.dut.u_io_div4_meas.u_meas
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisable 126 Covered T7,T8,T5
StDisabling 120 Covered T5,T6,T1
StEnable 113 Covered T5,T6,T1
StEnabling 107 Covered T5,T6,T1


transitionsLine No.CoveredTests
StDisable->StEnabling 107 Covered T5,T6,T1
StDisabling->StDisable 126 Covered T5,T6,T1
StEnable->StDisabling 120 Covered T5,T6,T1
StEnabling->StEnable 113 Covered T5,T6,T1



Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 88 2 2 100.00
CASE 103 8 8 100.00
IF 183 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T7,T8,T5
0 Covered T7,T8,T5


LineNo. Expression -1-: 103 case (state_q) -2-: 106 if (en_i) -3-: 112 if (en_ref_sync) -4-: 119 if ((!en_i)) -5-: 125 if ((!en_ref_sync))

Branches:
-1--2--3--4--5-StatusTests
StDisable 1 - - - Covered T5,T6,T1
StDisable 0 - - - Covered T5,T6,T1
StEnabling - 1 - - Covered T5,T6,T1
StEnabling - 0 - - Covered T5,T6,T1
StEnable - - 1 - Covered T5,T6,T1
StEnable - - 0 - Covered T5,T6,T1
StDisabling - - - 1 Covered T5,T6,T1
StDisabling - - - 0 Covered T5,T6,T1


LineNo. Expression -1-: 183 if ((!rst_ni)) -2-: 186 if (((!cnt_en) && (|cnt))) -3-: 189 if (valid_o) -4-: 192 if (cnt_ovfl) -5-: 194 if (cnt_en)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T7,T8,T5
0 1 - - - Covered T5,T6,T1
0 0 1 - - Covered T5,T6,T1
0 0 0 1 - Covered T5,T1,T2
0 0 0 0 1 Covered T5,T6,T1
0 0 0 0 0 Covered T7,T8,T5


Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 2 66.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 2 66.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MaxWidth_A 105534361 0 0 0
RefCntVal_A 805 805 0 0
gen_timeout_assert.ClkRatios_A 805 805 0 0


MaxWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 105534361 0 0 0

RefCntVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

gen_timeout_assert.ClkRatios_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS8833100.00
ALWAYS1001212100.00
CONT_ASSIGN16311100.00
ALWAYS1831313100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
89 1 1
91 1 1
100 1 1
101 1 1
103 1 1
106 1 1
107 1 1
MISSING_ELSE
112 1 1
113 1 1
MISSING_ELSE
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
MISSING_ELSE
163 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
195 1 1
MISSING_ELSE
199 1 1
200 1 1
201 1 1


Cond Coverage for Instance : tb.dut.u_main_meas.u_meas
TotalCoveredPercent
Conditions1515100.00
Logical1515100.00
Non-Logical00
Event00

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT7,T8,T5
11CoveredT5,T6,T1

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT5,T6,T1
11CoveredT5,T6,T1

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------
-1--2-StatusTests
01CoveredT5,T2,T3
10CoveredT5,T6,T1
11CoveredT5,T2,T3

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---
-1--2-StatusTests
00CoveredT7,T8,T5
01CoveredT5,T2,T3
10CoveredT5,T2,T3

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------
-1--2-StatusTests
01CoveredT7,T8,T5
10CoveredT5,T6,T1
11CoveredT2,T11,T12

FSM Coverage for Instance : tb.dut.u_main_meas.u_meas
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisable 126 Covered T7,T8,T5
StDisabling 120 Covered T5,T6,T1
StEnable 113 Covered T5,T6,T1
StEnabling 107 Covered T5,T6,T1


transitionsLine No.CoveredTests
StDisable->StEnabling 107 Covered T5,T6,T1
StDisabling->StDisable 126 Covered T5,T6,T1
StEnable->StDisabling 120 Covered T5,T6,T1
StEnabling->StEnable 113 Covered T5,T6,T1



Branch Coverage for Instance : tb.dut.u_main_meas.u_meas
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 88 2 2 100.00
CASE 103 8 8 100.00
IF 183 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T7,T8,T5
0 Covered T7,T8,T5


LineNo. Expression -1-: 103 case (state_q) -2-: 106 if (en_i) -3-: 112 if (en_ref_sync) -4-: 119 if ((!en_i)) -5-: 125 if ((!en_ref_sync))

Branches:
-1--2--3--4--5-StatusTests
StDisable 1 - - - Covered T5,T6,T1
StDisable 0 - - - Covered T5,T6,T1
StEnabling - 1 - - Covered T5,T6,T1
StEnabling - 0 - - Covered T5,T6,T1
StEnable - - 1 - Covered T5,T6,T1
StEnable - - 0 - Covered T5,T6,T1
StDisabling - - - 1 Covered T5,T6,T1
StDisabling - - - 0 Covered T5,T6,T1


LineNo. Expression -1-: 183 if ((!rst_ni)) -2-: 186 if (((!cnt_en) && (|cnt))) -3-: 189 if (valid_o) -4-: 192 if (cnt_ovfl) -5-: 194 if (cnt_en)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T7,T8,T5
0 1 - - - Covered T5,T6,T1
0 0 1 - - Covered T5,T6,T1
0 0 0 1 - Covered T5,T2,T3
0 0 0 0 1 Covered T5,T6,T1
0 0 0 0 0 Covered T7,T8,T5


Assert Coverage for Instance : tb.dut.u_main_meas.u_meas
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 2 66.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 2 66.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MaxWidth_A 453594436 0 0 0
RefCntVal_A 805 805 0 0
gen_timeout_assert.ClkRatios_A 805 805 0 0


MaxWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 453594436 0 0 0

RefCntVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

gen_timeout_assert.ClkRatios_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS8833100.00
ALWAYS1001212100.00
CONT_ASSIGN16311100.00
ALWAYS1831313100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20011100.00
CONT_ASSIGN20111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
89 1 1
91 1 1
100 1 1
101 1 1
103 1 1
106 1 1
107 1 1
MISSING_ELSE
112 1 1
113 1 1
MISSING_ELSE
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
MISSING_ELSE
163 1 1
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
195 1 1
MISSING_ELSE
199 1 1
200 1 1
201 1 1


Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas
TotalCoveredPercent
Conditions1515100.00
Logical1515100.00
Non-Logical00
Event00

 LINE       186
 EXPRESSION (((!cnt_en)) && ((|cnt)))
             -----1-----    ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT7,T8,T5
11CoveredT5,T6,T1

 LINE       199
 EXPRESSION (valid & ((|cnt)))
             --1--   ----2---
-1--2-StatusTests
01CoveredT5,T6,T1
10CoveredT5,T6,T1
11CoveredT5,T6,T1

 LINE       200
 EXPRESSION (valid_o & ((cnt > max_cnt) | cnt_ovfl))
             ---1---   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T6,T1
11CoveredT1,T2,T3

 LINE       200
 SUB-EXPRESSION ((cnt > max_cnt) | cnt_ovfl)
                 -------1-------   ----2---
-1--2-StatusTests
00CoveredT7,T8,T5
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       201
 EXPRESSION (valid_o & (cnt < min_cnt))
             ---1---   -------2-------
-1--2-StatusTests
01CoveredT7,T8,T5
10CoveredT5,T6,T1
11CoveredT2,T10,T13

FSM Coverage for Instance : tb.dut.u_usb_meas.u_meas
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 4 4 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisable 126 Covered T7,T8,T5
StDisabling 120 Covered T5,T6,T1
StEnable 113 Covered T5,T6,T1
StEnabling 107 Covered T5,T6,T1


transitionsLine No.CoveredTests
StDisable->StEnabling 107 Covered T5,T6,T1
StDisabling->StDisable 126 Covered T5,T6,T1
StEnable->StDisabling 120 Covered T5,T6,T1
StEnabling->StEnable 113 Covered T5,T6,T1



Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 88 2 2 100.00
CASE 103 8 8 100.00
IF 183 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_meas.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T7,T8,T5
0 Covered T7,T8,T5


LineNo. Expression -1-: 103 case (state_q) -2-: 106 if (en_i) -3-: 112 if (en_ref_sync) -4-: 119 if ((!en_i)) -5-: 125 if ((!en_ref_sync))

Branches:
-1--2--3--4--5-StatusTests
StDisable 1 - - - Covered T5,T6,T1
StDisable 0 - - - Covered T5,T6,T1
StEnabling - 1 - - Covered T5,T6,T1
StEnabling - 0 - - Covered T5,T6,T1
StEnable - - 1 - Covered T5,T6,T1
StEnable - - 0 - Covered T5,T6,T1
StDisabling - - - 1 Covered T5,T6,T1
StDisabling - - - 0 Covered T5,T6,T1


LineNo. Expression -1-: 183 if ((!rst_ni)) -2-: 186 if (((!cnt_en) && (|cnt))) -3-: 189 if (valid_o) -4-: 192 if (cnt_ovfl) -5-: 194 if (cnt_en)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T7,T8,T5
0 1 - - - Covered T5,T6,T1
0 0 1 - - Covered T5,T6,T1
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T5,T6,T1
0 0 0 0 0 Covered T7,T8,T5


Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 2 66.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 2 66.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MaxWidth_A 217552577 0 0 0
RefCntVal_A 805 805 0 0
gen_timeout_assert.ClkRatios_A 805 805 0 0


MaxWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217552577 0 0 0

RefCntVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

gen_timeout_assert.ClkRatios_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%