Module Definition
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Module : clkmgr_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.49 100.00 97.96 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.91 100.00 99.65 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.91 100.00 99.65 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.63 98.39 95.37 100.00 97.91 96.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_fault 100.00 100.00
u_alert_test_recov_fault 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_div2_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_div4_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_usb_peri_en 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_aes_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_hmac_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_kmac_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_otbn_hint 100.00 100.00 100.00 100.00
u_clk_hints_status_clk_main_aes_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_hmac_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_kmac_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_otbn_val 92.59 77.78 100.00 100.00
u_extclk_ctrl_hi_speed_sel 100.00 100.00 100.00 100.00
u_extclk_ctrl_regwen 100.00 100.00 100.00 100.00
u_extclk_ctrl_sel 100.00 100.00 100.00 100.00
u_extclk_status 100.00 100.00
u_fatal_err_code_idle_cnt 96.30 88.89 100.00 100.00
u_fatal_err_code_reg_intg 96.30 88.89 100.00 100.00
u_fatal_err_code_shadow_storage_err 96.30 88.89 100.00 100.00
u_io_div2_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_div2_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_io_div2_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_en_cdc 92.36 97.74 86.76 94.92 90.00
u_io_div4_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_io_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_jitter_enable 100.00 100.00 100.00 100.00
u_jitter_regwen 100.00 100.00 100.00 100.00
u_main_meas_ctrl_en 100.00 100.00 100.00 100.00
u_main_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_main_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_main_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_measure_ctrl_regwen 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_recov_err_code_io_div2_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div2_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div4_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div4_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_main_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_main_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_shadow_update_err 97.22 100.00 91.67 100.00
u_recov_err_code_usb_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_usb_timeout_err 100.00 100.00 100.00 100.00
u_reg_if 98.98 97.14 98.80 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_usb_meas_ctrl_en 100.00 100.00 100.00 100.00
u_usb_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_usb_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_usb_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_usb_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_usb_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : clkmgr_reg_top
Line No.TotalCoveredPercent
TOTAL244244100.00
ALWAYS8244100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
ALWAYS27744100.00
CONT_ASSIGN30711100.00
ALWAYS32033100.00
CONT_ASSIGN34911100.00
ALWAYS36344100.00
CONT_ASSIGN39311100.00
ALWAYS40633100.00
CONT_ASSIGN43511100.00
ALWAYS44944100.00
CONT_ASSIGN47911100.00
ALWAYS49233100.00
CONT_ASSIGN52111100.00
ALWAYS53544100.00
CONT_ASSIGN56511100.00
ALWAYS57833100.00
CONT_ASSIGN60711100.00
ALWAYS62144100.00
CONT_ASSIGN65111100.00
ALWAYS66433100.00
CONT_ASSIGN69311100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN71511100.00
CONT_ASSIGN73111100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN141011100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN144511100.00
CONT_ASSIGN156811100.00
CONT_ASSIGN157111100.00
CONT_ASSIGN160311100.00
CONT_ASSIGN172611100.00
CONT_ASSIGN172911100.00
CONT_ASSIGN176111100.00
CONT_ASSIGN188411100.00
CONT_ASSIGN188711100.00
CONT_ASSIGN191811100.00
ALWAYS24242323100.00
CONT_ASSIGN244911100.00
ALWAYS245311100.00
CONT_ASSIGN247911100.00
CONT_ASSIGN248111100.00
CONT_ASSIGN248311100.00
CONT_ASSIGN248411100.00
CONT_ASSIGN248611100.00
CONT_ASSIGN248711100.00
CONT_ASSIGN248911100.00
CONT_ASSIGN249111100.00
CONT_ASSIGN249211100.00
CONT_ASSIGN249311100.00
CONT_ASSIGN249511100.00
CONT_ASSIGN249611100.00
CONT_ASSIGN249811100.00
CONT_ASSIGN249911100.00
CONT_ASSIGN250111100.00
CONT_ASSIGN250311100.00
CONT_ASSIGN250511100.00
CONT_ASSIGN250711100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251211100.00
CONT_ASSIGN251411100.00
CONT_ASSIGN251611100.00
CONT_ASSIGN251711100.00
CONT_ASSIGN251911100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252311100.00
CONT_ASSIGN252611100.00
CONT_ASSIGN252811100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253211100.00
CONT_ASSIGN253411100.00
CONT_ASSIGN253511100.00
CONT_ASSIGN253811100.00
CONT_ASSIGN254011100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254411100.00
CONT_ASSIGN254611100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255211100.00
CONT_ASSIGN255411100.00
CONT_ASSIGN255611100.00
CONT_ASSIGN255811100.00
CONT_ASSIGN256011100.00
CONT_ASSIGN256211100.00
CONT_ASSIGN256411100.00
CONT_ASSIGN256611100.00
CONT_ASSIGN256811100.00
CONT_ASSIGN257011100.00
CONT_ASSIGN257211100.00
ALWAYS25762323100.00
ALWAYS26034747100.00
ALWAYS271733100.00
ALWAYS272533100.00
CONT_ASSIGN273311100.00
CONT_ASSIGN273611100.00
CONT_ASSIGN274811100.00
CONT_ASSIGN276311100.00
ALWAYS27651212100.00
CONT_ASSIGN281011100.00
CONT_ASSIGN281111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
MISSING_ELSE
91 1 1
103 1 1
104 1 1
132 1 1
133 1 1
277 1 1
278 1 1
279 1 1
280 1 1
307 1 1
320 1 1
321 1 1
322 1 1
349 1 1
363 1 1
364 1 1
365 1 1
366 1 1
393 1 1
406 1 1
407 1 1
408 1 1
435 1 1
449 1 1
450 1 1
451 1 1
452 1 1
479 1 1
492 1 1
493 1 1
494 1 1
521 1 1
535 1 1
536 1 1
537 1 1
538 1 1
565 1 1
578 1 1
579 1 1
580 1 1
607 1 1
621 1 1
622 1 1
623 1 1
624 1 1
651 1 1
664 1 1
665 1 1
666 1 1
693 1 1
700 1 1
715 1 1
731 1 1
765 1 1
1253 1 1
1256 1 1
1287 1 1
1410 1 1
1413 1 1
1445 1 1
1568 1 1
1571 1 1
1603 1 1
1726 1 1
1729 1 1
1761 1 1
1884 1 1
1887 1 1
1918 1 1
2424 1 1
2425 1 1
2426 1 1
2427 1 1
2428 1 1
2429 1 1
2430 1 1
2431 1 1
2432 1 1
2433 1 1
2434 1 1
2435 1 1
2436 1 1
2437 1 1
2438 1 1
2439 1 1
2440 1 1
2441 1 1
2442 1 1
2443 1 1
2444 1 1
2445 1 1
2446 1 1
2449 1 1
2453 1 1
2479 1 1
2481 1 1
2483 1 1
2484 1 1
2486 1 1
2487 1 1
2489 1 1
2491 1 1
2492 1 1
2493 1 1
2495 1 1
2496 1 1
2498 1 1
2499 1 1
2501 1 1
2503 1 1
2505 1 1
2507 1 1
2508 1 1
2510 1 1
2512 1 1
2514 1 1
2516 1 1
2517 1 1
2519 1 1
2520 1 1
2522 1 1
2523 1 1
2526 1 1
2528 1 1
2529 1 1
2532 1 1
2534 1 1
2535 1 1
2538 1 1
2540 1 1
2541 1 1
2544 1 1
2546 1 1
2547 1 1
2550 1 1
2552 1 1
2554 1 1
2556 1 1
2558 1 1
2560 1 1
2562 1 1
2564 1 1
2566 1 1
2568 1 1
2570 1 1
2572 1 1
2576 1 1
2577 1 1
2578 1 1
2579 1 1
2580 1 1
2581 1 1
2582 1 1
2583 1 1
2584 1 1
2585 1 1
2586 1 1
2587 1 1
2588 1 1
2589 1 1
2590 1 1
2591 1 1
2592 1 1
2593 1 1
2594 1 1
2595 1 1
2596 1 1
2597 1 1
2598 1 1
2603 1 1
2604 1 1
2606 1 1
2607 1 1
2611 1 1
2615 1 1
2616 1 1
2620 1 1
2624 1 1
2628 1 1
2632 1 1
2633 1 1
2634 1 1
2635 1 1
2639 1 1
2640 1 1
2641 1 1
2642 1 1
2646 1 1
2647 1 1
2648 1 1
2649 1 1
2653 1 1
2657 1 1
2660 1 1
2663 1 1
2666 1 1
2669 1 1
2672 1 1
2675 1 1
2678 1 1
2681 1 1
2684 1 1
2687 1 1
2688 1 1
2689 1 1
2690 1 1
2691 1 1
2692 1 1
2693 1 1
2694 1 1
2695 1 1
2696 1 1
2697 1 1
2701 1 1
2702 1 1
2703 1 1
2717 1 1
2718 1 1
2720 1 1
2725 1 1
2726 1 1
2728 1 1
2733 1 1
2736 1 1
2748 1 1
2763 1 1
2765 1 1
2766 1 1
2768 1 1
2771 1 1
2774 1 1
2777 1 1
2780 1 1
2783 1 1
2786 1 1
2789 1 1
2792 1 1
2795 1 1
2810 1 1
2811 1 1


Cond Coverage for Module : clkmgr_reg_top
TotalCoveredPercent
Conditions29428897.96
Logical29428897.96
Non-Logical00
Event00

 LINE       72
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT2,T10,T13
11CoveredT6,T7,T8

 LINE       84
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT38,T39,T40
10CoveredT92,T93,T94

 LINE       91
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT38,T39,T40
010CoveredT92,T93,T94
100CoveredT38,T39,T40

 LINE       133
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT92,T93,T94
010CoveredT2,T10,T13
100CoveredT2,T10,T13

 LINE       765
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T5,T95
11CoveredT6,T7,T8

 LINE       1256
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1287
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1413
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1445
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1571
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1603
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1729
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1761
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1887
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1918
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       2425
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT18,T2,T32

 LINE       2426
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       2427
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT20,T2,T32

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT18,T2,T32

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T25,T18

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT25,T26,T20

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT25,T20,T2

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT25,T2,T21

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T18

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T18

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T5

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T20

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T18

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T4,T1

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T5

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T5

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T4,T1

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T20

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T18

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T1,T20

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT20,T2,T70

 LINE       2449
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       2449
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       2453
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT2,T10,T13

 LINE       2453
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT6,T7,T8
22 (addr_hit[21] & ((|(4'...CoveredT20,T2,T70
21 (addr_hit[20] & ((|(4'...CoveredT1,T2,T32
20 (addr_hit[19] & ((|(4'...CoveredT4,T20,T5
19 (addr_hit[18] & ((|(4'...CoveredT4,T1,T20
18 (addr_hit[17] & ((|(4'...CoveredT8,T4,T18
17 (addr_hit[16] & ((|(4'...CoveredT4,T1,T5
16 (addr_hit[15] & ((|(4'...CoveredT4,T5,T2
15 (addr_hit[14] & ((|(4'...CoveredT8,T4,T1
14 (addr_hit[13] & ((|(4'...CoveredT4,T18,T20
13 (addr_hit[12] & ((|(4'...CoveredT4,T1,T20
12 (addr_hit[11] & ((|(4'...CoveredT4,T5,T2
11 (addr_hit[10] & ((|(4'...CoveredT4,T1,T18
10 (addr_hit[9] & ((|(4'b...CoveredT4,T1,T2
9 (addr_hit[8] & ((|(4'b...CoveredT2,T21,T23
8 (addr_hit[7] & ((|(4'b...CoveredT25,T2,T69
7 (addr_hit[6] & ((|(4'b...CoveredT20,T2,T32
6 (addr_hit[5] & ((|(4'b...CoveredT8,T25,T18
5 (addr_hit[4] & ((|(4'b...CoveredT2,T32,T69
4 (addr_hit[3] & ((|(4'b...CoveredT20,T2,T70
3 (addr_hit[2] & ((|(4'b...CoveredT6,T7,T8
2 (addr_hit[1] & ((|(4'b...CoveredT4,T5,T2
1 (addr_hit[0] & ((|(4'b...CoveredT2,T32,T28

 LINE       2453
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT18,T2,T32
11CoveredT2,T32,T28

 LINE       2453
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT4,T5,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT8,T25,T4
10CoveredT6,T7,T8
11CoveredT6,T7,T8

 LINE       2453
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT2,T32,T69
11CoveredT20,T2,T70

 LINE       2453
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT18,T2,T32
11CoveredT2,T32,T69

 LINE       2453
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT25,T2,T37
11CoveredT8,T25,T18

 LINE       2453
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT25,T26,T20
11CoveredT20,T2,T32

 LINE       2453
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT25,T20,T2
11CoveredT25,T2,T69

 LINE       2453
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT25,T2,T21
11CoveredT2,T21,T23

 LINE       2453
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T18
11CoveredT4,T1,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T18
11CoveredT4,T1,T18

 LINE       2453
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT4,T5,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T20
11CoveredT4,T1,T20

 LINE       2453
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT4,T18,T20

 LINE       2453
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T20
11CoveredT8,T4,T1

 LINE       2453
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT4,T5,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       2453
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT8,T4,T18

 LINE       2453
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T20
11CoveredT4,T1,T20

 LINE       2453
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T18
11CoveredT4,T20,T5

 LINE       2453
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT8,T1,T20
11CoveredT1,T2,T32

 LINE       2453
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT20,T2,T70
11CoveredT20,T2,T70

 LINE       2479
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT18,T2,T32
110CoveredT2,T10,T13
111CoveredT18,T32,T33

 LINE       2484
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T7,T8
110CoveredT2,T10,T13
111CoveredT6,T7,T8

 LINE       2487
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T7,T8
110CoveredT2,T10,T13
111CoveredT6,T7,T8

 LINE       2492
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT19,T20,T2
110CoveredT96,T97,T98
111CoveredT2,T70,T99

 LINE       2493
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT18,T2,T32
110CoveredT2,T10,T13
111CoveredT73,T51,T74

 LINE       2496
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T25,T18
110CoveredT2,T10,T13
111CoveredT25,T2,T37

 LINE       2499
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT25,T26,T18
110CoveredT2,T10,T13
111CoveredT25,T26,T2

 LINE       2508
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT25,T20,T2
110CoveredT2,T10,T13
111CoveredT25,T2,T21

 LINE       2517
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2520
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2522
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110Not Covered
111CoveredT4,T5,T2

 LINE       2523
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2526
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T20
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2528
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT92,T100
111CoveredT4,T5,T2

 LINE       2529
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2532
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T4,T1
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2534
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110CoveredT101,T102
111CoveredT4,T5,T2

 LINE       2535
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2538
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2540
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T4,T1
110CoveredT92,T103,T104
111CoveredT4,T5,T2

 LINE       2541
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T4,T1
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2544
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T20
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2546
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT94,T105
111CoveredT4,T5,T2

 LINE       2547
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2550
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T1,T20
110CoveredT2,T10,T13
111CoveredT1,T2,T3

 LINE       2733
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------
-1--2-StatusTests
01CoveredT51,T52,T53
10CoveredT4,T106,T107
11CoveredT6,T7,T8

 LINE       2763
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT8,T18,T19
10CoveredT4,T1,T5

Branch Coverage for Module : clkmgr_reg_top
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 2449 2 2 100.00
IF 82 3 3 100.00
CASE 2604 23 23 100.00
IF 2717 2 2 100.00
IF 2725 2 2 100.00
CASE 2766 11 11 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 2449 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 82 if ((!rst_ni)) -2-: 84 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T6,T7,T8
0 1 Covered T38,T39,T40
0 0 Covered T6,T7,T8


LineNo. Expression -1-: 2604 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T6,T7,T24
addr_hit[1] Covered T6,T7,T8
addr_hit[2] Covered T6,T7,T8
addr_hit[3] Covered T6,T7,T24
addr_hit[4] Covered T6,T7,T24
addr_hit[5] Covered T6,T7,T8
addr_hit[6] Covered T6,T7,T24
addr_hit[7] Covered T6,T7,T24
addr_hit[8] Covered T6,T7,T24
addr_hit[9] Covered T6,T7,T24
addr_hit[10] Covered T6,T7,T24
addr_hit[11] Covered T6,T7,T24
addr_hit[12] Covered T6,T7,T24
addr_hit[13] Covered T6,T7,T24
addr_hit[14] Covered T6,T7,T8
addr_hit[15] Covered T6,T7,T24
addr_hit[16] Covered T6,T7,T24
addr_hit[17] Covered T6,T7,T8
addr_hit[18] Covered T6,T7,T24
addr_hit[19] Covered T6,T7,T24
addr_hit[20] Covered T6,T7,T8
addr_hit[21] Covered T6,T7,T24
default Covered T6,T7,T8


LineNo. Expression -1-: 2717 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 2725 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 2766 case (1'b1)

Branches:
-1-StatusTests
addr_hit[10] Covered T6,T7,T24
addr_hit[11] Covered T6,T7,T24
addr_hit[12] Covered T6,T7,T24
addr_hit[13] Covered T6,T7,T24
addr_hit[14] Covered T6,T7,T8
addr_hit[15] Covered T6,T7,T24
addr_hit[16] Covered T6,T7,T24
addr_hit[17] Covered T6,T7,T8
addr_hit[18] Covered T6,T7,T24
addr_hit[19] Covered T6,T7,T24
default Covered T6,T7,T8


Assert Coverage for Module : clkmgr_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 170731694 868942 0 0
reAfterRv 170731694 868942 0 0
rePulse 170731694 201626 0 0
wePulse 170731694 667316 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 170731694 868942 0 0
T1 41393 334 0 0
T4 69716 517 0 0
T6 1480 31 0 0
T7 1797 43 0 0
T8 775 7 0 0
T17 1190 22 0 0
T18 1260 12 0 0
T24 1917 16 0 0
T25 2054 81 0 0
T26 767 7 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 170731694 868942 0 0
T1 41393 334 0 0
T4 69716 517 0 0
T6 1480 31 0 0
T7 1797 43 0 0
T8 775 7 0 0
T17 1190 22 0 0
T18 1260 12 0 0
T24 1917 16 0 0
T25 2054 81 0 0
T26 767 7 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 170731694 201626 0 0
T1 41393 38 0 0
T4 69716 264 0 0
T5 0 144 0 0
T6 1480 10 0 0
T7 1797 14 0 0
T8 775 2 0 0
T17 1190 7 0 0
T18 1260 0 0 0
T20 0 18 0 0
T24 1917 5 0 0
T25 2054 42 0 0
T26 767 0 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 170731694 667316 0 0
T1 41393 296 0 0
T4 69716 253 0 0
T6 1480 21 0 0
T7 1797 29 0 0
T8 775 5 0 0
T17 1190 15 0 0
T18 1260 12 0 0
T24 1917 11 0 0
T25 2054 39 0 0
T26 767 7 0 0

Line Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
TOTAL244244100.00
ALWAYS8244100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
ALWAYS27744100.00
CONT_ASSIGN30711100.00
ALWAYS32033100.00
CONT_ASSIGN34911100.00
ALWAYS36344100.00
CONT_ASSIGN39311100.00
ALWAYS40633100.00
CONT_ASSIGN43511100.00
ALWAYS44944100.00
CONT_ASSIGN47911100.00
ALWAYS49233100.00
CONT_ASSIGN52111100.00
ALWAYS53544100.00
CONT_ASSIGN56511100.00
ALWAYS57833100.00
CONT_ASSIGN60711100.00
ALWAYS62144100.00
CONT_ASSIGN65111100.00
ALWAYS66433100.00
CONT_ASSIGN69311100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN71511100.00
CONT_ASSIGN73111100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN141011100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN144511100.00
CONT_ASSIGN156811100.00
CONT_ASSIGN157111100.00
CONT_ASSIGN160311100.00
CONT_ASSIGN172611100.00
CONT_ASSIGN172911100.00
CONT_ASSIGN176111100.00
CONT_ASSIGN188411100.00
CONT_ASSIGN188711100.00
CONT_ASSIGN191811100.00
ALWAYS24242323100.00
CONT_ASSIGN244911100.00
ALWAYS245311100.00
CONT_ASSIGN247911100.00
CONT_ASSIGN248111100.00
CONT_ASSIGN248311100.00
CONT_ASSIGN248411100.00
CONT_ASSIGN248611100.00
CONT_ASSIGN248711100.00
CONT_ASSIGN248911100.00
CONT_ASSIGN249111100.00
CONT_ASSIGN249211100.00
CONT_ASSIGN249311100.00
CONT_ASSIGN249511100.00
CONT_ASSIGN249611100.00
CONT_ASSIGN249811100.00
CONT_ASSIGN249911100.00
CONT_ASSIGN250111100.00
CONT_ASSIGN250311100.00
CONT_ASSIGN250511100.00
CONT_ASSIGN250711100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251211100.00
CONT_ASSIGN251411100.00
CONT_ASSIGN251611100.00
CONT_ASSIGN251711100.00
CONT_ASSIGN251911100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252311100.00
CONT_ASSIGN252611100.00
CONT_ASSIGN252811100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253211100.00
CONT_ASSIGN253411100.00
CONT_ASSIGN253511100.00
CONT_ASSIGN253811100.00
CONT_ASSIGN254011100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254411100.00
CONT_ASSIGN254611100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255211100.00
CONT_ASSIGN255411100.00
CONT_ASSIGN255611100.00
CONT_ASSIGN255811100.00
CONT_ASSIGN256011100.00
CONT_ASSIGN256211100.00
CONT_ASSIGN256411100.00
CONT_ASSIGN256611100.00
CONT_ASSIGN256811100.00
CONT_ASSIGN257011100.00
CONT_ASSIGN257211100.00
ALWAYS25762323100.00
ALWAYS26034747100.00
ALWAYS271733100.00
ALWAYS272533100.00
CONT_ASSIGN273311100.00
CONT_ASSIGN273611100.00
CONT_ASSIGN274811100.00
CONT_ASSIGN276311100.00
ALWAYS27651212100.00
CONT_ASSIGN281011100.00
CONT_ASSIGN281111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
82 1 1
83 1 1
84 1 1
85 1 1
MISSING_ELSE
91 1 1
103 1 1
104 1 1
132 1 1
133 1 1
277 1 1
278 1 1
279 1 1
280 1 1
307 1 1
320 1 1
321 1 1
322 1 1
349 1 1
363 1 1
364 1 1
365 1 1
366 1 1
393 1 1
406 1 1
407 1 1
408 1 1
435 1 1
449 1 1
450 1 1
451 1 1
452 1 1
479 1 1
492 1 1
493 1 1
494 1 1
521 1 1
535 1 1
536 1 1
537 1 1
538 1 1
565 1 1
578 1 1
579 1 1
580 1 1
607 1 1
621 1 1
622 1 1
623 1 1
624 1 1
651 1 1
664 1 1
665 1 1
666 1 1
693 1 1
700 1 1
715 1 1
731 1 1
765 1 1
1253 1 1
1256 1 1
1287 1 1
1410 1 1
1413 1 1
1445 1 1
1568 1 1
1571 1 1
1603 1 1
1726 1 1
1729 1 1
1761 1 1
1884 1 1
1887 1 1
1918 1 1
2424 1 1
2425 1 1
2426 1 1
2427 1 1
2428 1 1
2429 1 1
2430 1 1
2431 1 1
2432 1 1
2433 1 1
2434 1 1
2435 1 1
2436 1 1
2437 1 1
2438 1 1
2439 1 1
2440 1 1
2441 1 1
2442 1 1
2443 1 1
2444 1 1
2445 1 1
2446 1 1
2449 1 1
2453 1 1
2479 1 1
2481 1 1
2483 1 1
2484 1 1
2486 1 1
2487 1 1
2489 1 1
2491 1 1
2492 1 1
2493 1 1
2495 1 1
2496 1 1
2498 1 1
2499 1 1
2501 1 1
2503 1 1
2505 1 1
2507 1 1
2508 1 1
2510 1 1
2512 1 1
2514 1 1
2516 1 1
2517 1 1
2519 1 1
2520 1 1
2522 1 1
2523 1 1
2526 1 1
2528 1 1
2529 1 1
2532 1 1
2534 1 1
2535 1 1
2538 1 1
2540 1 1
2541 1 1
2544 1 1
2546 1 1
2547 1 1
2550 1 1
2552 1 1
2554 1 1
2556 1 1
2558 1 1
2560 1 1
2562 1 1
2564 1 1
2566 1 1
2568 1 1
2570 1 1
2572 1 1
2576 1 1
2577 1 1
2578 1 1
2579 1 1
2580 1 1
2581 1 1
2582 1 1
2583 1 1
2584 1 1
2585 1 1
2586 1 1
2587 1 1
2588 1 1
2589 1 1
2590 1 1
2591 1 1
2592 1 1
2593 1 1
2594 1 1
2595 1 1
2596 1 1
2597 1 1
2598 1 1
2603 1 1
2604 1 1
2606 1 1
2607 1 1
2611 1 1
2615 1 1
2616 1 1
2620 1 1
2624 1 1
2628 1 1
2632 1 1
2633 1 1
2634 1 1
2635 1 1
2639 1 1
2640 1 1
2641 1 1
2642 1 1
2646 1 1
2647 1 1
2648 1 1
2649 1 1
2653 1 1
2657 1 1
2660 1 1
2663 1 1
2666 1 1
2669 1 1
2672 1 1
2675 1 1
2678 1 1
2681 1 1
2684 1 1
2687 1 1
2688 1 1
2689 1 1
2690 1 1
2691 1 1
2692 1 1
2693 1 1
2694 1 1
2695 1 1
2696 1 1
2697 1 1
2701 1 1
2702 1 1
2703 1 1
2717 1 1
2718 1 1
2720 1 1
2725 1 1
2726 1 1
2728 1 1
2733 1 1
2736 1 1
2748 1 1
2763 1 1
2765 1 1
2766 1 1
2768 1 1
2771 1 1
2774 1 1
2777 1 1
2780 1 1
2783 1 1
2786 1 1
2789 1 1
2792 1 1
2795 1 1
2810 1 1
2811 1 1


Cond Coverage for Instance : tb.dut.u_reg
TotalCoveredPercent
Conditions28928899.65
Logical28928899.65
Non-Logical00
Event00

 LINE       72
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT2,T10,T13
11CoveredT6,T7,T8

 LINE       84
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT38,T39,T40
10CoveredT92,T93,T94

 LINE       91
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT38,T39,T40
010CoveredT92,T93,T94
100CoveredT38,T39,T40

 LINE       133
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT92,T93,T94
010CoveredT2,T10,T13
100CoveredT2,T10,T13

 LINE       765
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T5,T95
11CoveredT6,T7,T8

 LINE       1256
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1287
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1413
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1445
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1571
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1603
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1729
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1761
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1887
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       1918
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------
-1--2-StatusTests
01CoveredT4,T5,T2
10CoveredT4,T5,T95
11CoveredT4,T1,T5

 LINE       2425
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT18,T2,T32

 LINE       2426
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       2427
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT20,T2,T32

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT18,T2,T32

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T25,T18

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT25,T26,T20

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT25,T20,T2

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT25,T2,T21

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T18

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T18

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T5

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T20

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T18

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T4,T1

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T5

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T5

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T4,T1

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T20

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT4,T1,T18

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT8,T1,T20

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT20,T2,T70

 LINE       2449
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT6,T7,T8

 LINE       2449
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT6,T7,T8
10CoveredT6,T7,T8

 LINE       2453
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT2,T10,T13

 LINE       2453
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT6,T7,T8
22 (addr_hit[21] & ((|(4'...CoveredT20,T2,T70
21 (addr_hit[20] & ((|(4'...CoveredT1,T2,T32
20 (addr_hit[19] & ((|(4'...CoveredT4,T20,T5
19 (addr_hit[18] & ((|(4'...CoveredT4,T1,T20
18 (addr_hit[17] & ((|(4'...CoveredT8,T4,T18
17 (addr_hit[16] & ((|(4'...CoveredT4,T1,T5
16 (addr_hit[15] & ((|(4'...CoveredT4,T5,T2
15 (addr_hit[14] & ((|(4'...CoveredT8,T4,T1
14 (addr_hit[13] & ((|(4'...CoveredT4,T18,T20
13 (addr_hit[12] & ((|(4'...CoveredT4,T1,T20
12 (addr_hit[11] & ((|(4'...CoveredT4,T5,T2
11 (addr_hit[10] & ((|(4'...CoveredT4,T1,T18
10 (addr_hit[9] & ((|(4'b...CoveredT4,T1,T2
9 (addr_hit[8] & ((|(4'b...CoveredT2,T21,T23
8 (addr_hit[7] & ((|(4'b...CoveredT25,T2,T69
7 (addr_hit[6] & ((|(4'b...CoveredT20,T2,T32
6 (addr_hit[5] & ((|(4'b...CoveredT8,T25,T18
5 (addr_hit[4] & ((|(4'b...CoveredT2,T32,T69
4 (addr_hit[3] & ((|(4'b...CoveredT20,T2,T70
3 (addr_hit[2] & ((|(4'b...CoveredT6,T7,T8
2 (addr_hit[1] & ((|(4'b...CoveredT4,T5,T2
1 (addr_hit[0] & ((|(4'b...CoveredT2,T32,T28

 LINE       2453
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT18,T2,T32
11CoveredT2,T32,T28

 LINE       2453
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT4,T5,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT8,T25,T4
10CoveredT6,T7,T8
11CoveredT6,T7,T8

 LINE       2453
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT2,T32,T69
11CoveredT20,T2,T70

 LINE       2453
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT18,T2,T32
11CoveredT2,T32,T69

 LINE       2453
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT25,T2,T37
11CoveredT8,T25,T18

 LINE       2453
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT25,T26,T20
11CoveredT20,T2,T32

 LINE       2453
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT25,T20,T2
11CoveredT25,T2,T69

 LINE       2453
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT25,T2,T21
11CoveredT2,T21,T23

 LINE       2453
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T18
11CoveredT4,T1,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T18
11CoveredT4,T1,T18

 LINE       2453
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT4,T5,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T20
11CoveredT4,T1,T20

 LINE       2453
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT4,T18,T20

 LINE       2453
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T20
11CoveredT8,T4,T1

 LINE       2453
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT4,T5,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT4,T1,T5

 LINE       2453
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T5
11CoveredT8,T4,T18

 LINE       2453
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T20
11CoveredT4,T1,T20

 LINE       2453
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT4,T1,T18
11CoveredT4,T20,T5

 LINE       2453
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT8,T1,T20
11CoveredT1,T2,T32

 LINE       2453
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT20,T2,T70
11CoveredT20,T2,T70

 LINE       2479
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT18,T2,T32
110CoveredT2,T10,T13
111CoveredT18,T32,T33

 LINE       2484
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T7,T8
110CoveredT2,T10,T13
111CoveredT6,T7,T8

 LINE       2487
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT6,T7,T8
110CoveredT2,T10,T13
111CoveredT6,T7,T8

 LINE       2492
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT19,T20,T2
110CoveredT96,T97,T98
111CoveredT2,T70,T99

 LINE       2493
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT18,T2,T32
110CoveredT2,T10,T13
111CoveredT73,T51,T74

 LINE       2496
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T25,T18
110CoveredT2,T10,T13
111CoveredT25,T2,T37

 LINE       2499
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT25,T26,T18
110CoveredT2,T10,T13
111CoveredT25,T26,T2

 LINE       2508
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT25,T20,T2
110CoveredT2,T10,T13
111CoveredT25,T2,T21

 LINE       2517
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2520
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2522
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110Not Covered
111CoveredT4,T5,T2

 LINE       2523
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2526
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T20
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2528
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT92,T100
111CoveredT4,T5,T2

 LINE       2529
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2532
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T4,T1
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2534
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110CoveredT101,T102
111CoveredT4,T5,T2

 LINE       2535
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2538
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T5
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2540
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T4,T1
110CoveredT92,T103,T104
111CoveredT4,T5,T2

 LINE       2541
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T4,T1
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2544
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T20
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2546
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT94,T105
111CoveredT4,T5,T2

 LINE       2547
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT4,T1,T18
110CoveredT2,T10,T13
111CoveredT4,T1,T5

 LINE       2550
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T7,T8
101CoveredT8,T1,T20
110CoveredT2,T10,T13
111CoveredT1,T2,T3

 LINE       2733
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------
-1--2-StatusTests
01CoveredT51,T52,T53
10CoveredT4,T106,T107
11CoveredT6,T7,T8

 LINE       2763
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT8,T18,T19
10CoveredT4,T1,T5

Branch Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 2449 2 2 100.00
IF 82 3 3 100.00
CASE 2604 23 23 100.00
IF 2717 2 2 100.00
IF 2725 2 2 100.00
CASE 2766 11 11 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 2449 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 82 if ((!rst_ni)) -2-: 84 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T6,T7,T8
0 1 Covered T38,T39,T40
0 0 Covered T6,T7,T8


LineNo. Expression -1-: 2604 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T6,T7,T24
addr_hit[1] Covered T6,T7,T8
addr_hit[2] Covered T6,T7,T8
addr_hit[3] Covered T6,T7,T24
addr_hit[4] Covered T6,T7,T24
addr_hit[5] Covered T6,T7,T8
addr_hit[6] Covered T6,T7,T24
addr_hit[7] Covered T6,T7,T24
addr_hit[8] Covered T6,T7,T24
addr_hit[9] Covered T6,T7,T24
addr_hit[10] Covered T6,T7,T24
addr_hit[11] Covered T6,T7,T24
addr_hit[12] Covered T6,T7,T24
addr_hit[13] Covered T6,T7,T24
addr_hit[14] Covered T6,T7,T8
addr_hit[15] Covered T6,T7,T24
addr_hit[16] Covered T6,T7,T24
addr_hit[17] Covered T6,T7,T8
addr_hit[18] Covered T6,T7,T24
addr_hit[19] Covered T6,T7,T24
addr_hit[20] Covered T6,T7,T8
addr_hit[21] Covered T6,T7,T24
default Covered T6,T7,T8


LineNo. Expression -1-: 2717 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 2725 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8


LineNo. Expression -1-: 2766 case (1'b1)

Branches:
-1-StatusTests
addr_hit[10] Covered T6,T7,T24
addr_hit[11] Covered T6,T7,T24
addr_hit[12] Covered T6,T7,T24
addr_hit[13] Covered T6,T7,T24
addr_hit[14] Covered T6,T7,T8
addr_hit[15] Covered T6,T7,T24
addr_hit[16] Covered T6,T7,T24
addr_hit[17] Covered T6,T7,T8
addr_hit[18] Covered T6,T7,T24
addr_hit[19] Covered T6,T7,T24
default Covered T6,T7,T8


Assert Coverage for Instance : tb.dut.u_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 170731694 868942 0 0
reAfterRv 170731694 868942 0 0
rePulse 170731694 201626 0 0
wePulse 170731694 667316 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 170731694 868942 0 0
T1 41393 334 0 0
T4 69716 517 0 0
T6 1480 31 0 0
T7 1797 43 0 0
T8 775 7 0 0
T17 1190 22 0 0
T18 1260 12 0 0
T24 1917 16 0 0
T25 2054 81 0 0
T26 767 7 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 170731694 868942 0 0
T1 41393 334 0 0
T4 69716 517 0 0
T6 1480 31 0 0
T7 1797 43 0 0
T8 775 7 0 0
T17 1190 22 0 0
T18 1260 12 0 0
T24 1917 16 0 0
T25 2054 81 0 0
T26 767 7 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 170731694 201626 0 0
T1 41393 38 0 0
T4 69716 264 0 0
T5 0 144 0 0
T6 1480 10 0 0
T7 1797 14 0 0
T8 775 2 0 0
T17 1190 7 0 0
T18 1260 0 0 0
T20 0 18 0 0
T24 1917 5 0 0
T25 2054 42 0 0
T26 767 0 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 170731694 667316 0 0
T1 41393 296 0 0
T4 69716 253 0 0
T6 1480 21 0 0
T7 1797 29 0 0
T8 775 5 0 0
T17 1190 15 0 0
T18 1260 12 0 0
T24 1917 11 0 0
T25 2054 39 0 0
T26 767 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%