Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1707316940	1537516	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1707316940	293606	0	0
SrcBusyKnown_A	1707316940	1679890540	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1707316940	1537516	0	0
T1	413930	936	0	0
T2	2581910	14561	0	0
T3	0	5037	0	0
T4	697160	2729	0	0
T5	121830	604	0	0
T10	0	6260	0	0
T17	11900	0	0	0
T18	12600	0	0	0
T19	8820	0	0	0
T20	20010	0	0	0
T21	19850	0	0	0
T26	7670	0	0	0
T28	0	2066	0	0
T29	0	1540	0	0
T30	0	2140	0	0
T31	0	966	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1046342	1045170	0	0
T4	395192	35718	0	0
T6	25138	24648	0	0
T7	11990	11270	0	0
T8	27152	25976	0	0
T17	27312	26186	0	0
T18	16172	15004	0	0
T24	12556	11360	0	0
T25	13404	12186	0	0
T26	96988	96248	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1707316940	293606	0	0
T1	413930	280	0	0
T2	2581910	2980	0	0
T3	0	1480	0	0
T4	697160	312	0	0
T5	121830	178	0	0
T10	0	780	0	0
T17	11900	0	0	0
T18	12600	0	0	0
T19	8820	0	0	0
T20	20010	0	0	0
T21	19850	0	0	0
T26	7670	0	0	0
T28	0	400	0	0
T29	0	300	0	0
T30	0	260	0	0
T31	0	180	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1707316940	1679890540	0	0
T1	413930	413440	0	0
T4	697160	56580	0	0
T6	14800	14490	0	0
T7	17970	16770	0	0
T8	7750	7370	0	0
T17	11900	11350	0	0
T18	12600	11640	0	0
T24	19170	17110	0	0
T25	20540	18510	0	0
T26	7670	7610	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	95503	0	0
DstReqKnown_A	476296458	471734721	0	0
SrcAckBusyChk_A	170731694	26366	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	95503	0	0
T1	41393	67	0	0
T2	258191	1022	0	0
T3	0	371	0	0
T4	69716	114	0	0
T5	12183	30	0	0
T10	0	376	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	144	0	0
T29	0	106	0	0
T30	0	134	0	0
T31	0	67	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476296458	471734721	0	0
T1	158947	158757	0	0
T4	66926	5421	0	0
T6	3741	3661	0	0
T7	1815	1694	0	0
T8	4139	3935	0	0
T17	4080	3891	0	0
T18	2469	2279	0	0
T24	1896	1693	0	0
T25	2054	1851	0	0
T26	14741	14620	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	26366	0	0
T1	41393	28	0	0
T2	258191	295	0	0
T3	0	148	0	0
T4	69716	22	0	0
T5	12183	12	0	0
T10	0	75	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	137206	0	0
DstReqKnown_A	237292562	236155300	0	0
SrcAckBusyChk_A	170731694	26366	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	137206	0	0
T1	41393	96	0	0
T2	258191	1436	0	0
T3	0	519	0	0
T4	69716	183	0	0
T5	12183	42	0	0
T10	0	598	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	207	0	0
T29	0	153	0	0
T30	0	215	0	0
T31	0	98	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237292562	236155300	0	0
T1	79447	79378	0	0
T4	18327	2713	0	0
T6	2041	2013	0	0
T7	922	887	0	0
T8	2039	1991	0	0
T17	2191	2136	0	0
T18	1208	1139	0	0
T24	974	919	0	0
T25	987	925	0	0
T26	7351	7310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	26366	0	0
T1	41393	28	0	0
T2	258191	295	0	0
T3	0	148	0	0
T4	69716	22	0	0
T5	12183	12	0	0
T10	0	75	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	221981	0	0
DstReqKnown_A	118645665	118077132	0	0
SrcAckBusyChk_A	170731694	26366	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	221981	0	0
T1	41393	138	0	0
T2	258191	2273	0	0
T3	0	741	0	0
T4	69716	318	0	0
T5	12183	60	0	0
T10	0	1068	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	331	0	0
T29	0	251	0	0
T30	0	375	0	0
T31	0	154	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118645665	118077132	0	0
T1	39724	39690	0	0
T4	9163	1356	0	0
T6	1020	1006	0	0
T7	460	443	0	0
T8	1019	995	0	0
T17	1095	1067	0	0
T18	604	570	0	0
T24	486	459	0	0
T25	494	463	0	0
T26	3676	3655	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	26366	0	0
T1	41393	28	0	0
T2	258191	295	0	0
T3	0	148	0	0
T4	69716	22	0	0
T5	12183	12	0	0
T10	0	75	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	95351	0	0
DstReqKnown_A	507580748	502762290	0	0
SrcAckBusyChk_A	170731694	26366	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	95351	0	0
T1	41393	66	0	0
T2	258191	1023	0	0
T3	0	371	0	0
T4	69716	132	0	0
T5	12183	30	0	0
T10	0	364	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	141	0	0
T29	0	106	0	0
T30	0	131	0	0
T31	0	65	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507580748	502762290	0	0
T1	165576	165378	0	0
T4	69716	5658	0	0
T6	3897	3813	0	0
T7	1890	1764	0	0
T8	4310	4099	0	0
T17	4250	4053	0	0
T18	2571	2374	0	0
T24	1975	1763	0	0
T25	2140	1929	0	0
T26	15355	15229	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	26366	0	0
T1	41393	28	0	0
T2	258191	295	0	0
T3	0	148	0	0
T4	69716	22	0	0
T5	12183	12	0	0
T10	0	75	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	135647	0	0
DstReqKnown_A	243909956	241597082	0	0
SrcAckBusyChk_A	170731694	25879	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	135647	0	0
T1	41393	95	0	0
T2	258191	1447	0	0
T3	0	519	0	0
T4	69716	103	0	0
T5	12183	40	0	0
T10	0	605	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	207	0	0
T29	0	152	0	0
T30	0	218	0	0
T31	0	97	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243909956	241597082	0	0
T1	79477	79382	0	0
T4	33464	2711	0	0
T6	1870	1831	0	0
T7	908	847	0	0
T8	2069	1968	0	0
T17	2040	1946	0	0
T18	1234	1140	0	0
T24	947	846	0	0
T25	1027	925	0	0
T26	7371	7310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	25879	0	0
T1	41393	28	0	0
T2	258191	295	0	0
T3	0	148	0	0
T4	69716	11	0	0
T5	12183	10	0	0
T10	0	75	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	118580	0	0
DstReqKnown_A	476296458	471734721	0	0
SrcAckBusyChk_A	170731694	32552	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	118580	0	0
T1	41393	70	0	0
T2	258191	1046	0	0
T3	0	370	0	0
T4	69716	228	0	0
T5	12183	59	0	0
T10	0	405	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	145	0	0
T29	0	110	0	0
T30	0	134	0	0
T31	0	66	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476296458	471734721	0	0
T1	158947	158757	0	0
T4	66926	5421	0	0
T6	3741	3661	0	0
T7	1815	1694	0	0
T8	4139	3935	0	0
T17	4080	3891	0	0
T18	2469	2279	0	0
T24	1896	1693	0	0
T25	2054	1851	0	0
T26	14741	14620	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	32552	0	0
T1	41393	28	0	0
T2	258191	301	0	0
T3	0	148	0	0
T4	69716	44	0	0
T5	12183	24	0	0
T10	0	81	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	170028	0	0
DstReqKnown_A	237292562	236155300	0	0
SrcAckBusyChk_A	170731694	32501	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	170028	0	0
T1	41393	98	0	0
T2	258191	1475	0	0
T3	0	518	0	0
T4	69716	375	0	0
T5	12183	83	0	0
T10	0	650	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	208	0	0
T29	0	154	0	0
T30	0	214	0	0
T31	0	96	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237292562	236155300	0	0
T1	79447	79378	0	0
T4	18327	2713	0	0
T6	2041	2013	0	0
T7	922	887	0	0
T8	2039	1991	0	0
T17	2191	2136	0	0
T18	1208	1139	0	0
T24	974	919	0	0
T25	987	925	0	0
T26	7351	7310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	32501	0	0
T1	41393	28	0	0
T2	258191	301	0	0
T3	0	148	0	0
T4	69716	44	0	0
T5	12183	24	0	0
T10	0	81	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	275809	0	0
DstReqKnown_A	118645665	118077132	0	0
SrcAckBusyChk_A	170731694	32554	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	275809	0	0
T1	41393	139	0	0
T2	258191	2329	0	0
T3	0	740	0	0
T4	69716	659	0	0
T5	12183	118	0	0
T10	0	1143	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	333	0	0
T29	0	246	0	0
T30	0	374	0	0
T31	0	161	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118645665	118077132	0	0
T1	39724	39690	0	0
T4	9163	1356	0	0
T6	1020	1006	0	0
T7	460	443	0	0
T8	1019	995	0	0
T17	1095	1067	0	0
T18	604	570	0	0
T24	486	459	0	0
T25	494	463	0	0
T26	3676	3655	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	32554	0	0
T1	41393	28	0	0
T2	258191	301	0	0
T3	0	148	0	0
T4	69716	44	0	0
T5	12183	24	0	0
T10	0	81	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	117589	0	0
DstReqKnown_A	507580748	502762290	0	0
SrcAckBusyChk_A	170731694	32522	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	117589	0	0
T1	41393	68	0	0
T2	258191	1033	0	0
T3	0	370	0	0
T4	69716	268	0	0
T5	12183	59	0	0
T10	0	396	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	141	0	0
T29	0	106	0	0
T30	0	131	0	0
T31	0	65	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507580748	502762290	0	0
T1	165576	165378	0	0
T4	69716	5658	0	0
T6	3897	3813	0	0
T7	1890	1764	0	0
T8	4310	4099	0	0
T17	4250	4053	0	0
T18	2571	2374	0	0
T24	1975	1763	0	0
T25	2140	1929	0	0
T26	15355	15229	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	32522	0	0
T1	41393	28	0	0
T2	258191	301	0	0
T3	0	148	0	0
T4	69716	44	0	0
T5	12183	24	0	0
T10	0	81	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T1,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T7,T8
0	1	-	Covered	T4,T1,T5
0	0	1	Covered	T4,T1,T5
0	0	0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170731694	169822	0	0
DstReqKnown_A	243909956	241597082	0	0
SrcAckBusyChk_A	170731694	32134	0	0
SrcBusyKnown_A	170731694	167989054	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	169822	0	0
T1	41393	99	0	0
T2	258191	1477	0	0
T3	0	518	0	0
T4	69716	349	0	0
T5	12183	83	0	0
T10	0	655	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	209	0	0
T29	0	156	0	0
T30	0	214	0	0
T31	0	97	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	243909956	241597082	0	0
T1	79477	79382	0	0
T4	33464	2711	0	0
T6	1870	1831	0	0
T7	908	847	0	0
T8	2069	1968	0	0
T17	2040	1946	0	0
T18	1234	1140	0	0
T24	947	846	0	0
T25	1027	925	0	0
T26	7371	7310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	32134	0	0
T1	41393	28	0	0
T2	258191	301	0	0
T3	0	148	0	0
T4	69716	37	0	0
T5	12183	24	0	0
T10	0	81	0	0
T17	1190	0	0	0
T18	1260	0	0	0
T19	882	0	0	0
T20	2001	0	0	0
T21	1985	0	0	0
T26	767	0	0	0
T28	0	40	0	0
T29	0	30	0	0
T30	0	26	0	0
T31	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170731694	167989054	0	0
T1	41393	41344	0	0
T4	69716	5658	0	0
T6	1480	1449	0	0
T7	1797	1677	0	0
T8	775	737	0	0
T17	1190	1135	0	0
T18	1260	1164	0	0
T24	1917	1711	0	0
T25	2054	1851	0	0
T26	767	761	0	0