Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	887246	0	0
SrcPulseCheck_M	2147483647	882253	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	887246
T1	0	224
T2	0	1571
T3	0	6255
T4	349262	150
T5	525308	202
T6	57780	61
T7	801920	1036
T9	11830	0
T11	0	1018
T12	0	272
T18	0	436
T21	0	30
T25	72296	0
T26	15447	0
T27	29095	0
T28	11942	0
T32	0	614
T33	12532	0
T55	26616	1
T56	12284	1
T57	19590	1
T58	8648	1
T59	12958	1
T63	6318	1
T64	12914	0
T72	0	297
T120	20276	3
T121	11480	2
T122	4105	0
T123	7831	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	882253
T1	0	224
T2	0	1469
T3	0	6255
T4	203546	150
T5	130640	202
T6	15996	61
T7	262139	1036
T9	6923	0
T11	0	1018
T12	0	272
T18	0	436
T21	0	30
T25	18670	0
T26	7862	0
T27	9046	0
T28	3962	0
T32	0	614
T33	5235	0
T55	11018	1
T56	24162	1
T57	8340	1
T58	7692	1
T59	26882	1
T63	5484	1
T64	24484	0
T72	0	297
T120	36786	3
T121	30890	2
T122	3578	0
T123	3540	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	371322015	24003	0	0
SrcPulseCheck_M	157802665	24003	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	371322015	24003
T1	0	16
T2	0	95
T3	0	316
T4	85657	30
T5	151841	40
T6	15827	2
T7	181232	40
T9	2375	0
T11	0	74
T18	0	16
T21	0	6
T25	17534	0
T26	3236	0
T27	7295	0
T28	3011	0
T33	2930	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	24003
T1	0	16
T2	0	95
T3	0	316
T4	89229	30
T5	39542	40
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	6
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	371322015	29687	0	0
SrcPulseCheck_M	157802665	29700	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	371322015	29687
T1	0	16
T2	0	100
T3	0	321
T4	85657	60
T5	151841	80
T6	15827	2
T7	181232	40
T9	2375	0
T11	0	74
T18	0	16
T21	0	12
T25	17534	0
T26	3236	0
T27	7295	0
T28	3011	0
T33	2930	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	29700
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	29672	0	0
SrcPulseCheck_M	371322015	29692	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	29672
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	371322015	29692
T1	0	16
T2	0	100
T3	0	321
T4	85657	60
T5	151841	80
T6	15827	2
T7	181232	40
T9	2375	0
T11	0	74
T18	0	16
T21	0	12
T25	17534	0
T26	3236	0
T27	7295	0
T28	3011	0
T33	2930	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	185032127	24003	0	0
SrcPulseCheck_M	157802665	24003	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	185032127	24003
T1	0	16
T2	0	95
T3	0	316
T4	24328	30
T5	50216	40
T6	7860	2
T7	90549	40
T9	1289	0
T11	0	74
T18	0	16
T21	0	6
T25	9906	0
T26	1794	0
T27	3580	0
T28	1452	0
T33	1453	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	24003
T1	0	16
T2	0	95
T3	0	316
T4	89229	30
T5	39542	40
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	6
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	185032127	29550	0	0
SrcPulseCheck_M	157802665	29588	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	185032127	29550
T1	0	16
T2	0	100
T3	0	321
T4	24328	60
T5	50216	80
T6	7860	2
T7	90549	40
T9	1289	0
T11	0	74
T18	0	16
T21	0	12
T25	9906	0
T26	1794	0
T27	3580	0
T28	1452	0
T33	1453	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	29588
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	29544	0	0
SrcPulseCheck_M	185032127	29557	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	29544
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	185032127	29557
T1	0	16
T2	0	100
T3	0	321
T4	24328	60
T5	50216	80
T6	7860	2
T7	90549	40
T9	1289	0
T11	0	74
T18	0	16
T21	0	12
T25	9906	0
T26	1794	0
T27	3580	0
T28	1452	0
T33	1453	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92515457	24003	0	0
SrcPulseCheck_M	157802665	24003	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92515457	24003
T1	0	16
T2	0	95
T3	0	316
T4	12163	30
T5	25105	40
T6	3930	2
T7	45275	40
T9	642	0
T11	0	74
T18	0	16
T21	0	6
T25	4952	0
T26	895	0
T27	1790	0
T28	726	0
T33	726	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	24003
T1	0	16
T2	0	95
T3	0	316
T4	89229	30
T5	39542	40
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	6
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	92515457	29487	0	0
SrcPulseCheck_M	157802665	29531	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	92515457	29487
T1	0	16
T2	0	100
T3	0	321
T4	12163	60
T5	25105	80
T6	3930	2
T7	45275	40
T9	642	0
T11	0	74
T18	0	16
T21	0	12
T25	4952	0
T26	895	0
T27	1790	0
T28	726	0
T33	726	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	29531
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	29484	0	0
SrcPulseCheck_M	92515457	29494	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	29484
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92515457	29494
T1	0	16
T2	0	100
T3	0	321
T4	12163	60
T5	25105	80
T6	3930	2
T7	45275	40
T9	642	0
T11	0	74
T18	0	16
T21	0	12
T25	4952	0
T26	895	0
T27	1790	0
T28	726	0
T33	726	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	397202964	24003	0	0
SrcPulseCheck_M	157802665	24003	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	397202964	24003
T1	0	16
T2	0	95
T3	0	316
T4	89229	30
T5	158172	40
T6	10487	2
T7	218789	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	6
T25	18266	0
T26	3372	0
T27	7599	0
T28	3044	0
T33	3052	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	24003
T1	0	16
T2	0	95
T3	0	316
T4	89229	30
T5	39542	40
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	6
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	397202964	29596	0	0
SrcPulseCheck_M	157802665	29614	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	397202964	29596
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	158172	80
T6	10487	2
T7	218789	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	18266	0
T26	3372	0
T27	7599	0
T28	3044	0
T33	3052	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	29614
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	29585	0	0
SrcPulseCheck_M	397202964	29599	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	29585
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	397202964	29599
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	158172	80
T6	10487	2
T7	218789	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	18266	0
T26	3372	0
T27	7599	0
T28	3044	0
T33	3052	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T7,T5
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	190661799	23620	0	0
SrcPulseCheck_M	157802665	24003	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	190661799	23620
T1	0	16
T2	0	95
T3	0	316
T4	42831	15
T5	75923	32
T6	7914	2
T7	113661	40
T9	1187	0
T11	0	74
T18	0	16
T21	0	3
T25	8767	0
T26	1618	0
T27	3647	0
T28	1504	0
T33	1465	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	24003
T1	0	16
T2	0	95
T3	0	316
T4	89229	30
T5	39542	40
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	6
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	190661799	29416	0	0
SrcPulseCheck_M	157802665	29587	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	190661799	29416
T1	0	16
T2	0	100
T3	0	321
T4	42831	45
T5	75923	80
T6	7914	2
T7	113661	40
T9	1187	0
T11	0	74
T18	0	16
T21	0	12
T25	8767	0
T26	1618	0
T27	3647	0
T28	1504	0
T33	1465	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	157802665	29587
T1	0	16
T2	0	100
T3	0	321
T4	89229	60
T5	39542	80
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T4,T7
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	29323	0	0
SrcPulseCheck_M	190661799	29453	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	29323
T1	0	16
T2	0	100
T3	0	321
T4	89229	45
T5	39542	79
T6	3956	2
T7	84977	40
T9	2473	0
T11	0	74
T18	0	16
T21	0	12
T25	1826	0
T26	2562	0
T27	1671	0
T28	805	0
T33	1465	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	190661799	29453
T1	0	16
T2	0	100
T3	0	321
T4	42831	45
T5	75923	80
T6	7914	2
T7	113661	40
T9	1187	0
T11	0	74
T18	0	16
T21	0	12
T25	8767	0
T26	1618	0
T27	3647	0
T28	1504	0
T33	1465	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T56,T60
1	0	Covered	T55,T56,T60
1	1	Covered	T63,T124,T125

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T56,T60
1	0	Covered	T63,T124,T125
1	1	Covered	T55,T56,T60

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	30	0	0
SrcPulseCheck_M	371322015	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	30
T55	13308	1
T56	6142	1
T60	2794	1
T62	6823	2
T63	3159	3
T120	10138	1
T122	4105	1
T124	6124	4
T126	8650	1
T127	9817	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	371322015	30
T55	13169	1
T56	24569	1
T60	20633	1
T62	93585	2
T63	6066	3
T120	38928	1
T122	8210	1
T124	20997	4
T126	11070	1
T127	9423	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T57,T56
1	0	Covered	T55,T57,T56
1	1	Covered	T63

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T57,T56
1	0	Covered	T63
1	1	Covered	T55,T57,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	28	0	0
SrcPulseCheck_M	371322015	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	28
T55	13308	2
T56	6142	1
T57	9795	1
T60	2794	1
T62	6823	1
T63	3159	2
T120	10138	2
T122	4105	1
T123	7831	1
T127	9817	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	371322015	28
T55	13169	2
T56	24569	1
T57	9403	1
T60	20633	1
T62	93585	1
T63	6066	2
T120	38928	2
T122	8210	1
T123	7749	1
T127	9423	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T57,T56
1	0	Covered	T55,T57,T56
1	1	Covered	T120,T124,T128

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T57,T56
1	0	Covered	T120,T124,T128
1	1	Covered	T55,T57,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	31	0	0
SrcPulseCheck_M	185032127	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	31
T55	13308	1
T56	6142	1
T57	9795	1
T58	4324	1
T59	6479	1
T63	3159	1
T64	6457	2
T120	10138	3
T121	5740	2
T122	4105	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	185032127	31
T55	5509	1
T56	12081	1
T57	4170	1
T58	3846	1
T59	13441	1
T63	2742	1
T64	12242	2
T120	18393	3
T121	15445	2
T122	3578	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T57,T56
1	0	Covered	T55,T57,T56
1	1	Covered	T63,T125,T129

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T57,T56
1	0	Covered	T63,T125,T129
1	1	Covered	T55,T57,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	40	0	0
SrcPulseCheck_M	185032127	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	40
T55	13308	2
T56	6142	1
T57	9795	1
T58	4324	2
T59	6479	1
T63	3159	2
T64	6457	1
T120	10138	2
T121	5740	2
T123	7831	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	185032127	40
T55	5509	2
T56	12081	1
T57	4170	1
T58	3846	2
T59	13441	1
T63	2742	2
T64	12242	1
T120	18393	2
T121	15445	2
T123	3540	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T58,T63
1	0	Covered	T55,T58,T63
1	1	Covered	T55,T63,T62

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T58,T63
1	0	Covered	T55,T63,T62
1	1	Covered	T55,T58,T63

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	37	0	0
SrcPulseCheck_M	92515457	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	37
T55	13308	4
T58	4324	1
T61	10764	1
T62	6823	2
T63	3159	2
T120	10138	1
T126	8650	3
T127	9817	2
T130	5013	2
T131	17697	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92515457	37
T55	2752	4
T58	1921	1
T61	10276	1
T62	22965	2
T63	1370	2
T120	9196	1
T126	2356	3
T127	2131	2
T130	4823	2
T131	3903	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T58,T59
1	0	Covered	T55,T58,T59
1	1	Covered	T55,T63,T126

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T58,T59
1	0	Covered	T55,T63,T126
1	1	Covered	T55,T58,T59

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	39	0	0
SrcPulseCheck_M	92515457	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	39
T55	13308	4
T58	4324	2
T59	6479	1
T60	2794	1
T61	10764	1
T62	6823	2
T63	3159	2
T120	10138	2
T126	8650	4
T130	5013	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	92515457	39
T55	2752	4
T58	1921	2
T59	6719	1
T60	4831	1
T61	10276	1
T62	22965	2
T63	1370	2
T120	9196	2
T126	2356	4
T130	4823	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T54,T59,T60
1	0	Covered	T54,T59,T60
1	1	Covered	T132,T133,T134

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T54,T59,T60
1	0	Covered	T132,T133,T134
1	1	Covered	T54,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	43	0	0
SrcPulseCheck_M	397202964	43	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	43
T54	8270	1
T59	6479	1
T60	2794	1
T61	10764	1
T62	6823	1
T64	6457	1
T122	4105	1
T123	7831	1
T126	8650	2
T127	9817	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	397202964	43
T54	8438	1
T59	29449	1
T60	21494	1
T61	44851	1
T62	97488	1
T64	26904	1
T122	8552	1
T123	8072	1
T126	11533	2
T127	9817	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T59,T60
1	0	Covered	T55,T59,T60
1	1	Covered	T64,T135,T133

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T55,T59,T60
1	0	Covered	T64,T135,T133
1	1	Covered	T55,T59,T60

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	39	0	0
SrcPulseCheck_M	397202964	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	39
T55	13308	1
T59	6479	1
T60	2794	1
T61	10764	1
T62	6823	1
T64	6457	3
T122	4105	1
T126	8650	1
T128	12243	2
T131	17697	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	397202964	39
T55	13719	1
T59	29449	1
T60	21494	1
T61	44851	1
T62	97488	1
T64	26904	3
T122	8552	1
T126	11533	1
T128	12754	2
T131	18058	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T54,T57,T60
1	0	Covered	T54,T57,T60
1	1	Covered	T62,T127,T128

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T54,T57,T60
1	0	Covered	T62,T127,T128
1	1	Covered	T54,T57,T60

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	36	0	0
SrcPulseCheck_M	190661799	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	36
T54	8270	1
T57	9795	1
T60	2794	1
T61	10764	1
T62	6823	2
T64	6457	1
T120	10138	2
T121	5740	1
T123	7831	1
T127	9817	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	190661799	36
T54	4051	1
T57	4702	1
T60	10317	1
T61	21528	1
T62	46794	2
T64	12914	1
T120	19466	2
T121	16209	1
T123	3875	1
T127	4712	4

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T54,T57,T60
1	0	Covered	T54,T57,T60
1	1	Covered	T57,T62,T127

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T54,T57,T60
1	0	Covered	T57,T62,T127
1	1	Covered	T54,T57,T60

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	157802665	39	0	0
SrcPulseCheck_M	190661799	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	157802665	39
T54	8270	1
T57	9795	2
T60	2794	1
T61	10764	2
T62	6823	3
T64	6457	1
T120	10138	1
T121	5740	1
T126	8650	1
T127	9817	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	190661799	39
T54	4051	1
T57	4702	2
T60	10317	1
T61	21528	2
T62	46794	3
T64	12914	1
T120	19466	1
T121	16209	1
T126	5535	1
T127	4712	5

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T5
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T5
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T5

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	368246313	87371	0	0
SrcPulseCheck_M	12678814	86181	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	368246313	87371
T1	0	44
T2	0	307
T3	0	1290
T4	85657	0
T5	151841	2
T6	15827	17
T7	181232	214
T9	2375	0
T11	0	199
T12	0	68
T18	0	91
T25	17534	0
T26	3236	0
T27	7295	0
T28	3011	0
T32	0	142
T33	2930	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12678814	86181
T1	0	44
T2	0	273
T3	0	1290
T4	190	0
T5	335	2
T6	59	17
T7	394	214
T9	172	0
T11	0	199
T12	0	68
T18	0	91
T25	1278	0
T26	236	0
T27	531	0
T28	225	0
T32	0	142
T33	213	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	183540877	87063	0	0
SrcPulseCheck_M	12678814	85875	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	183540877	87063
T1	0	44
T2	0	307
T3	0	1288
T4	24328	0
T5	50216	0
T6	7860	17
T7	90549	214
T9	1289	0
T11	0	199
T12	0	68
T18	0	91
T25	9906	0
T26	1794	0
T27	3580	0
T28	1452	0
T32	0	141
T33	1453	0
T72	0	87

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12678814	85875
T1	0	44
T2	0	273
T3	0	1288
T4	190	0
T5	335	0
T6	59	17
T7	394	214
T9	172	0
T11	0	199
T12	0	68
T18	0	91
T25	1278	0
T26	236	0
T27	531	0
T28	225	0
T32	0	141
T33	213	0
T72	0	87

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	91769832	86392	0	0
SrcPulseCheck_M	12678814	85207	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	91769832	86392
T1	0	44
T2	0	307
T3	0	1284
T4	12163	0
T5	25105	0
T6	3930	17
T7	45275	214
T9	642	0
T11	0	199
T12	0	68
T18	0	91
T25	4952	0
T26	895	0
T27	1790	0
T28	726	0
T32	0	130
T33	726	0
T72	0	87

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12678814	85207
T1	0	44
T2	0	273
T3	0	1284
T4	190	0
T5	335	0
T6	59	17
T7	394	214
T9	172	0
T11	0	199
T12	0	68
T18	0	91
T25	1278	0
T26	236	0
T27	531	0
T28	225	0
T32	0	130
T33	213	0
T72	0	87

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T1
1	0	Covered	T7,T1,T2
1	1	Covered	T6,T7,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	393998983	106023	0	0
SrcPulseCheck_M	12511094	105624	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	393998983	106023
T1	0	44
T2	0	355
T3	0	1435
T4	89229	0
T5	158172	0
T6	10487	4
T7	218789	274
T9	2473	0
T11	0	199
T12	0	68
T18	0	115
T25	18266	0
T26	3372	0
T27	7599	0
T28	3044	0
T32	0	201
T33	3052	0
T72	0	123

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12511094	105624
T1	0	44
T2	0	355
T3	0	1435
T4	190	0
T5	335	0
T6	47	4
T7	454	274
T9	172	0
T11	0	199
T12	0	68
T18	0	115
T25	1278	0
T26	236	0
T27	531	0
T28	225	0
T32	0	201
T33	213	0
T72	0	123

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T1
1	0	Covered	T7,T1,T2
1	1	Covered	T6,T7,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T6,T7,T1
1	0	Covered	T6,T7,T1
1	1	Covered	T6,T7,T1

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T8,T6,T9
0	Covered	T8,T6,T9

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	189123907	105059	0	0
SrcPulseCheck_M	12370688	103174	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	189123907	105059
T1	0	41
T2	0	331
T3	0	1524
T4	42831	0
T5	75923	0
T6	7914	16
T7	113661	310
T9	1187	0
T11	0	199
T12	0	64
T18	0	79
T25	8767	0
T26	1618	0
T27	3647	0
T28	1504	0
T32	0	185
T33	1465	0
T72	0	135

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	12370688	103174
T1	0	41
T2	0	331
T3	0	1524
T4	190	0
T5	335	0
T6	59	16
T7	490	310
T9	172	0
T11	0	199
T12	0	64
T18	0	79
T25	1278	0
T26	236	0
T27	531	0
T28	225	0
T32	0	185
T33	213	0
T72	0	135

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb