Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1578026650	1473614	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1578026650	267244	0	0
SrcBusyKnown_A	1578026650	1553656840	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578026650	1473614	0	0
T1	0	608	0	0
T2	0	4912	0	0
T3	0	12545	0	0
T4	892290	3703	0	0
T5	395420	2123	0	0
T6	39560	56	0	0
T7	849770	1706	0	0
T9	24730	0	0	0
T11	0	2483	0	0
T18	0	1322	0	0
T21	0	689	0	0
T25	18260	0	0	0
T26	25620	0	0	0
T27	16710	0	0	0
T28	8050	0	0	0
T33	14650	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	508416	28960	0	0
T5	922514	243082	0	0
T6	92036	90678	0	0
T7	1299012	1298058	0	0
T8	11616	10578	0	0
T9	15932	15046	0	0
T25	118850	117972	0	0
T26	21830	21102	0	0
T27	47822	46866	0	0
T28	19474	18476	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578026650	267244	0	0
T1	0	160	0	0
T2	0	975	0	0
T3	0	3185	0	0
T4	892290	420	0	0
T5	395420	584	0	0
T6	39560	20	0	0
T7	849770	400	0	0
T9	24730	0	0	0
T11	0	740	0	0
T18	0	160	0	0
T21	0	87	0	0
T25	18260	0	0	0
T26	25620	0	0	0
T27	16710	0	0	0
T28	8050	0	0	0
T33	14650	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1578026650	1553656840	0	0
T4	892290	45900	0	0
T5	395420	96350	0	0
T6	39560	38990	0	0
T7	849770	849140	0	0
T8	18570	16730	0	0
T9	24730	23040	0	0
T25	18260	18110	0	0
T26	25620	24550	0	0
T27	16710	16310	0	0
T28	8050	7600	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	89950	0	0
DstReqKnown_A	371322015	367358387	0	0
SrcAckBusyChk_A	157802665	24003	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	89950	0	0
T1	0	48	0	0
T2	0	326	0	0
T3	0	937	0	0
T4	89229	159	0	0
T5	39542	107	0	0
T6	3956	4	0	0
T7	84977	130	0	0
T9	2473	0	0	0
T11	0	184	0	0
T18	0	94	0	0
T21	0	30	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371322015	367358387	0	0
T4	85657	4394	0	0
T5	151841	36921	0	0
T6	15827	15596	0	0
T7	181232	181057	0	0
T8	1782	1607	0	0
T9	2375	2213	0	0
T25	17534	17386	0	0
T26	3236	3101	0	0
T27	7295	7119	0	0
T28	3011	2835	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	24003	0	0
T1	0	16	0	0
T2	0	95	0	0
T3	0	316	0	0
T4	89229	30	0	0
T5	39542	40	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	6	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	131940	0	0
DstReqKnown_A	185032127	184046260	0	0
SrcAckBusyChk_A	157802665	24003	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	131940	0	0
T1	0	61	0	0
T2	0	460	0	0
T3	0	1257	0	0
T4	89229	256	0	0
T5	39542	146	0	0
T6	3956	6	0	0
T7	84977	168	0	0
T9	2473	0	0	0
T11	0	258	0	0
T18	0	134	0	0
T21	0	49	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185032127	184046260	0	0
T4	24328	2200	0	0
T5	50216	18467	0	0
T6	7860	7798	0	0
T7	90549	90528	0	0
T8	852	804	0	0
T9	1289	1268	0	0
T25	9906	9865	0	0
T26	1794	1780	0	0
T27	3580	3559	0	0
T28	1452	1417	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	24003	0	0
T1	0	16	0	0
T2	0	95	0	0
T3	0	316	0	0
T4	89229	30	0	0
T5	39542	40	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	6	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	214584	0	0
DstReqKnown_A	92515457	92022649	0	0
SrcAckBusyChk_A	157802665	24003	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	214584	0	0
T1	0	88	0	0
T2	0	728	0	0
T3	0	1839	0	0
T4	89229	450	0	0
T5	39542	213	0	0
T6	3956	8	0	0
T7	84977	259	0	0
T9	2473	0	0	0
T11	0	365	0	0
T18	0	230	0	0
T21	0	82	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92515457	92022649	0	0
T4	12163	1099	0	0
T5	25105	9231	0	0
T6	3930	3899	0	0
T7	45275	45265	0	0
T8	426	402	0	0
T9	642	632	0	0
T25	4952	4931	0	0
T26	895	888	0	0
T27	1790	1780	0	0
T28	726	709	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	24003	0	0
T1	0	16	0	0
T2	0	95	0	0
T3	0	316	0	0
T4	89229	30	0	0
T5	39542	40	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	6	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	88850	0	0
DstReqKnown_A	397202964	392943706	0	0
SrcAckBusyChk_A	157802665	24003	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	88850	0	0
T1	0	44	0	0
T2	0	319	0	0
T3	0	918	0	0
T4	89229	182	0	0
T5	39542	103	0	0
T6	3956	4	0	0
T7	84977	127	0	0
T9	2473	0	0	0
T11	0	184	0	0
T18	0	77	0	0
T21	0	28	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397202964	392943706	0	0
T4	89229	4590	0	0
T5	158172	38460	0	0
T6	10487	10247	0	0
T7	218789	218606	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	18266	18111	0	0
T26	3372	3231	0	0
T27	7599	7416	0	0
T28	3044	2861	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	24003	0	0
T1	0	16	0	0
T2	0	95	0	0
T3	0	316	0	0
T4	89229	30	0	0
T5	39542	40	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	6	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	129585	0	0
DstReqKnown_A	190661799	188623578	0	0
SrcAckBusyChk_A	157802665	23583	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	129585	0	0
T1	0	63	0	0
T2	0	555	0	0
T3	0	1249	0	0
T4	89229	149	0	0
T5	39542	123	0	0
T6	3956	6	0	0
T7	84977	168	0	0
T9	2473	0	0	0
T11	0	258	0	0
T18	0	124	0	0
T21	0	37	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190661799	188623578	0	0
T4	42831	2197	0	0
T5	75923	18462	0	0
T6	7914	7799	0	0
T7	113661	113573	0	0
T8	891	803	0	0
T9	1187	1106	0	0
T25	8767	8693	0	0
T26	1618	1551	0	0
T27	3647	3559	0	0
T28	1504	1416	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	23583	0	0
T1	0	16	0	0
T2	0	95	0	0
T3	0	316	0	0
T4	89229	15	0	0
T5	39542	25	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	3	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	112572	0	0
DstReqKnown_A	371322015	367358387	0	0
SrcAckBusyChk_A	157802665	29675	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	112572	0	0
T1	0	46	0	0
T2	0	342	0	0
T3	0	960	0	0
T4	89229	312	0	0
T5	39542	213	0	0
T6	3956	4	0	0
T7	84977	129	0	0
T9	2473	0	0	0
T11	0	181	0	0
T18	0	94	0	0
T21	0	57	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	371322015	367358387	0	0
T4	85657	4394	0	0
T5	151841	36921	0	0
T6	15827	15596	0	0
T7	181232	181057	0	0
T8	1782	1607	0	0
T9	2375	2213	0	0
T25	17534	17386	0	0
T26	3236	3101	0	0
T27	7295	7119	0	0
T28	3011	2835	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	29675	0	0
T1	0	16	0	0
T2	0	100	0	0
T3	0	321	0	0
T4	89229	60	0	0
T5	39542	80	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	12	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	164350	0	0
DstReqKnown_A	185032127	184046260	0	0
SrcAckBusyChk_A	157802665	29546	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	164350	0	0
T1	0	61	0	0
T2	0	484	0	0
T3	0	1277	0	0
T4	89229	508	0	0
T5	39542	292	0	0
T6	3956	6	0	0
T7	84977	171	0	0
T9	2473	0	0	0
T11	0	255	0	0
T18	0	133	0	0
T21	0	95	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185032127	184046260	0	0
T4	24328	2200	0	0
T5	50216	18467	0	0
T6	7860	7798	0	0
T7	90549	90528	0	0
T8	852	804	0	0
T9	1289	1268	0	0
T25	9906	9865	0	0
T26	1794	1780	0	0
T27	3580	3559	0	0
T28	1452	1417	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	29546	0	0
T1	0	16	0	0
T2	0	100	0	0
T3	0	321	0	0
T4	89229	60	0	0
T5	39542	80	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	12	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	268054	0	0
DstReqKnown_A	92515457	92022649	0	0
SrcAckBusyChk_A	157802665	29486	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	268054	0	0
T1	0	88	0	0
T2	0	774	0	0
T3	0	1892	0	0
T4	89229	890	0	0
T5	39542	426	0	0
T6	3956	8	0	0
T7	84977	261	0	0
T9	2473	0	0	0
T11	0	362	0	0
T18	0	232	0	0
T21	0	166	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92515457	92022649	0	0
T4	12163	1099	0	0
T5	25105	9231	0	0
T6	3930	3899	0	0
T7	45275	45265	0	0
T8	426	402	0	0
T9	642	632	0	0
T25	4952	4931	0	0
T26	895	888	0	0
T27	1790	1780	0	0
T28	726	709	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	29486	0	0
T1	0	16	0	0
T2	0	100	0	0
T3	0	321	0	0
T4	89229	60	0	0
T5	39542	80	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	12	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	110638	0	0
DstReqKnown_A	397202964	392943706	0	0
SrcAckBusyChk_A	157802665	29586	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	110638	0	0
T1	0	45	0	0
T2	0	340	0	0
T3	0	938	0	0
T4	89229	364	0	0
T5	39542	205	0	0
T6	3956	4	0	0
T7	84977	127	0	0
T9	2473	0	0	0
T11	0	181	0	0
T18	0	78	0	0
T21	0	54	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397202964	392943706	0	0
T4	89229	4590	0	0
T5	158172	38460	0	0
T6	10487	10247	0	0
T7	218789	218606	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	18266	18111	0	0
T26	3372	3231	0	0
T27	7599	7416	0	0
T28	3044	2861	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	29586	0	0
T1	0	16	0	0
T2	0	100	0	0
T3	0	321	0	0
T4	89229	60	0	0
T5	39542	80	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	12	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T6,T9
0	1	Unreachable
1	0	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T6,T9
0	1	-	Covered	T6,T4,T7
0	0	1	Covered	T6,T4,T7
0	0	0	Covered	T8,T6,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	157802665	163091	0	0
DstReqKnown_A	190661799	188623578	0	0
SrcAckBusyChk_A	157802665	29356	0	0
SrcBusyKnown_A	157802665	155365684	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	163091	0	0
T1	0	64	0	0
T2	0	584	0	0
T3	0	1278	0	0
T4	89229	433	0	0
T5	39542	295	0	0
T6	3956	6	0	0
T7	84977	166	0	0
T9	2473	0	0	0
T11	0	255	0	0
T18	0	126	0	0
T21	0	91	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190661799	188623578	0	0
T4	42831	2197	0	0
T5	75923	18462	0	0
T6	7914	7799	0	0
T7	113661	113573	0	0
T8	891	803	0	0
T9	1187	1106	0	0
T25	8767	8693	0	0
T26	1618	1551	0	0
T27	3647	3559	0	0
T28	1504	1416	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	29356	0	0
T1	0	16	0	0
T2	0	100	0	0
T3	0	321	0	0
T4	89229	45	0	0
T5	39542	79	0	0
T6	3956	2	0	0
T7	84977	40	0	0
T9	2473	0	0	0
T11	0	74	0	0
T18	0	16	0	0
T21	0	12	0	0
T25	1826	0	0	0
T26	2562	0	0	0
T27	1671	0	0	0
T28	805	0	0	0
T33	1465	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157802665	155365684	0	0
T4	89229	4590	0	0
T5	39542	9635	0	0
T6	3956	3899	0	0
T7	84977	84914	0	0
T8	1857	1673	0	0
T9	2473	2304	0	0
T25	1826	1811	0	0
T26	2562	2455	0	0
T27	1671	1631	0	0
T28	805	760	0	0