Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5727035 |
5721299 |
0 |
0 |
T2 |
5539091 |
5534364 |
0 |
0 |
T4 |
1097346 |
146546 |
0 |
0 |
T5 |
59956 |
58622 |
0 |
0 |
T6 |
46724 |
41291 |
0 |
0 |
T7 |
38679 |
32803 |
0 |
0 |
T16 |
56353 |
54019 |
0 |
0 |
T17 |
218722 |
215990 |
0 |
0 |
T18 |
50751 |
48439 |
0 |
0 |
T19 |
1451934 |
299181 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1026990450 |
1011241236 |
0 |
14490 |
T1 |
1290606 |
1289202 |
0 |
18 |
T2 |
1272396 |
1271196 |
0 |
18 |
T4 |
249894 |
15390 |
0 |
18 |
T5 |
5574 |
5418 |
0 |
18 |
T6 |
10674 |
9312 |
0 |
18 |
T7 |
9210 |
7746 |
0 |
18 |
T16 |
8148 |
7758 |
0 |
18 |
T17 |
21006 |
20694 |
0 |
18 |
T18 |
4722 |
4464 |
0 |
18 |
T19 |
231546 |
29766 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
1541587 |
1539909 |
0 |
21 |
T2 |
1475974 |
1474581 |
0 |
21 |
T4 |
298495 |
18367 |
0 |
21 |
T5 |
21073 |
20520 |
0 |
21 |
T6 |
12471 |
10881 |
0 |
21 |
T7 |
10138 |
8440 |
0 |
21 |
T16 |
18022 |
17178 |
0 |
21 |
T17 |
76486 |
75386 |
0 |
21 |
T18 |
17863 |
16923 |
0 |
21 |
T19 |
460012 |
59331 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
204186 |
0 |
0 |
T1 |
1541587 |
4 |
0 |
0 |
T2 |
1475974 |
4 |
0 |
0 |
T3 |
0 |
28 |
0 |
0 |
T4 |
298495 |
28 |
0 |
0 |
T5 |
20144 |
36 |
0 |
0 |
T6 |
12471 |
58 |
0 |
0 |
T7 |
10138 |
41 |
0 |
0 |
T12 |
0 |
693 |
0 |
0 |
T16 |
18022 |
12 |
0 |
0 |
T17 |
76486 |
270 |
0 |
0 |
T18 |
17863 |
12 |
0 |
0 |
T19 |
460012 |
52 |
0 |
0 |
T20 |
1435 |
0 |
0 |
0 |
T21 |
0 |
25 |
0 |
0 |
T31 |
0 |
104 |
0 |
0 |
T62 |
0 |
87 |
0 |
0 |
T67 |
0 |
76 |
0 |
0 |
T70 |
0 |
65 |
0 |
0 |
T81 |
0 |
156 |
0 |
0 |
T82 |
0 |
5 |
0 |
0 |
T108 |
0 |
127 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2894842 |
2892149 |
0 |
0 |
T2 |
2790721 |
2788548 |
0 |
0 |
T4 |
548957 |
112516 |
0 |
0 |
T5 |
33309 |
32645 |
0 |
0 |
T6 |
23579 |
21059 |
0 |
0 |
T7 |
19331 |
16578 |
0 |
0 |
T16 |
30183 |
29044 |
0 |
0 |
T17 |
121230 |
119871 |
0 |
0 |
T18 |
28166 |
27013 |
0 |
0 |
T19 |
760376 |
209481 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T21 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T21 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T21 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T21 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T21 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T21 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T21 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T21 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482496515 |
478165224 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
203578 |
203388 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
3719 |
3625 |
0 |
0 |
T6 |
1725 |
1508 |
0 |
0 |
T7 |
1380 |
1149 |
0 |
0 |
T16 |
2962 |
2827 |
0 |
0 |
T17 |
13448 |
13259 |
0 |
0 |
T18 |
3153 |
2990 |
0 |
0 |
T19 |
74094 |
9600 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482496515 |
478158231 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
203578 |
203385 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
3719 |
3622 |
0 |
3 |
T6 |
1725 |
1505 |
0 |
3 |
T7 |
1380 |
1146 |
0 |
3 |
T16 |
2962 |
2824 |
0 |
3 |
T17 |
13448 |
13256 |
0 |
3 |
T18 |
3153 |
2987 |
0 |
3 |
T19 |
74094 |
9561 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482496515 |
27841 |
0 |
0 |
T1 |
215101 |
0 |
0 |
0 |
T2 |
203578 |
0 |
0 |
0 |
T3 |
0 |
11 |
0 |
0 |
T4 |
41649 |
0 |
0 |
0 |
T5 |
3719 |
7 |
0 |
0 |
T6 |
1725 |
18 |
0 |
0 |
T7 |
1380 |
0 |
0 |
0 |
T16 |
2962 |
0 |
0 |
0 |
T17 |
13448 |
0 |
0 |
0 |
T18 |
3153 |
0 |
0 |
0 |
T19 |
74094 |
0 |
0 |
0 |
T21 |
0 |
12 |
0 |
0 |
T31 |
0 |
40 |
0 |
0 |
T62 |
0 |
43 |
0 |
0 |
T67 |
0 |
39 |
0 |
0 |
T70 |
0 |
31 |
0 |
0 |
T81 |
0 |
52 |
0 |
0 |
T108 |
0 |
53 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T21,T31 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T21,T31 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T21,T31 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T21,T31 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T21,T31 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T21,T31 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T21,T31 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T21,T31 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168540206 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
929 |
903 |
0 |
3 |
T6 |
1779 |
1552 |
0 |
3 |
T7 |
1535 |
1291 |
0 |
3 |
T16 |
1358 |
1293 |
0 |
3 |
T17 |
3501 |
3449 |
0 |
3 |
T18 |
787 |
744 |
0 |
3 |
T19 |
38591 |
4961 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
17390 |
0 |
0 |
T1 |
215101 |
0 |
0 |
0 |
T2 |
212066 |
0 |
0 |
0 |
T3 |
0 |
11 |
0 |
0 |
T4 |
41649 |
0 |
0 |
0 |
T6 |
1779 |
12 |
0 |
0 |
T7 |
1535 |
0 |
0 |
0 |
T12 |
0 |
693 |
0 |
0 |
T16 |
1358 |
0 |
0 |
0 |
T17 |
3501 |
0 |
0 |
0 |
T18 |
787 |
0 |
0 |
0 |
T19 |
38591 |
0 |
0 |
0 |
T20 |
1435 |
0 |
0 |
0 |
T21 |
0 |
7 |
0 |
0 |
T31 |
0 |
29 |
0 |
0 |
T62 |
0 |
4 |
0 |
0 |
T70 |
0 |
15 |
0 |
0 |
T81 |
0 |
50 |
0 |
0 |
T82 |
0 |
5 |
0 |
0 |
T108 |
0 |
33 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T21 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T21 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T21 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T21 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T21 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T21 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T21 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T21 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168540206 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
929 |
903 |
0 |
3 |
T6 |
1779 |
1552 |
0 |
3 |
T7 |
1535 |
1291 |
0 |
3 |
T16 |
1358 |
1293 |
0 |
3 |
T17 |
3501 |
3449 |
0 |
3 |
T18 |
787 |
744 |
0 |
3 |
T19 |
38591 |
4961 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
19279 |
0 |
0 |
T1 |
215101 |
0 |
0 |
0 |
T2 |
212066 |
0 |
0 |
0 |
T3 |
0 |
6 |
0 |
0 |
T4 |
41649 |
0 |
0 |
0 |
T5 |
929 |
7 |
0 |
0 |
T6 |
1779 |
8 |
0 |
0 |
T7 |
1535 |
0 |
0 |
0 |
T16 |
1358 |
0 |
0 |
0 |
T17 |
3501 |
0 |
0 |
0 |
T18 |
787 |
0 |
0 |
0 |
T19 |
38591 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T31 |
0 |
35 |
0 |
0 |
T62 |
0 |
40 |
0 |
0 |
T67 |
0 |
37 |
0 |
0 |
T70 |
0 |
19 |
0 |
0 |
T81 |
0 |
54 |
0 |
0 |
T108 |
0 |
41 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
512548110 |
0 |
0 |
T1 |
224071 |
223930 |
0 |
0 |
T2 |
212066 |
211983 |
0 |
0 |
T4 |
43387 |
27289 |
0 |
0 |
T5 |
3874 |
3819 |
0 |
0 |
T6 |
1797 |
1685 |
0 |
0 |
T7 |
1422 |
1281 |
0 |
0 |
T16 |
3086 |
3003 |
0 |
0 |
T17 |
14009 |
13897 |
0 |
0 |
T18 |
3284 |
3187 |
0 |
0 |
T19 |
77184 |
44115 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
512548110 |
0 |
0 |
T1 |
224071 |
223930 |
0 |
0 |
T2 |
212066 |
211983 |
0 |
0 |
T4 |
43387 |
27289 |
0 |
0 |
T5 |
3874 |
3819 |
0 |
0 |
T6 |
1797 |
1685 |
0 |
0 |
T7 |
1422 |
1281 |
0 |
0 |
T16 |
3086 |
3003 |
0 |
0 |
T17 |
14009 |
13897 |
0 |
0 |
T18 |
3284 |
3187 |
0 |
0 |
T19 |
77184 |
44115 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482496515 |
480348761 |
0 |
0 |
T1 |
215101 |
214966 |
0 |
0 |
T2 |
203578 |
203498 |
0 |
0 |
T4 |
41649 |
26202 |
0 |
0 |
T5 |
3719 |
3666 |
0 |
0 |
T6 |
1725 |
1618 |
0 |
0 |
T7 |
1380 |
1245 |
0 |
0 |
T16 |
2962 |
2882 |
0 |
0 |
T17 |
13448 |
13341 |
0 |
0 |
T18 |
3153 |
3059 |
0 |
0 |
T19 |
74094 |
42348 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482496515 |
480348761 |
0 |
0 |
T1 |
215101 |
214966 |
0 |
0 |
T2 |
203578 |
203498 |
0 |
0 |
T4 |
41649 |
26202 |
0 |
0 |
T5 |
3719 |
3666 |
0 |
0 |
T6 |
1725 |
1618 |
0 |
0 |
T7 |
1380 |
1245 |
0 |
0 |
T16 |
2962 |
2882 |
0 |
0 |
T17 |
13448 |
13341 |
0 |
0 |
T18 |
3153 |
3059 |
0 |
0 |
T19 |
74094 |
42348 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
240441259 |
240441259 |
0 |
0 |
T1 |
107483 |
107483 |
0 |
0 |
T2 |
101749 |
101749 |
0 |
0 |
T4 |
13103 |
13103 |
0 |
0 |
T5 |
1858 |
1858 |
0 |
0 |
T6 |
889 |
889 |
0 |
0 |
T7 |
623 |
623 |
0 |
0 |
T16 |
1441 |
1441 |
0 |
0 |
T17 |
6671 |
6671 |
0 |
0 |
T18 |
1530 |
1530 |
0 |
0 |
T19 |
21178 |
21178 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
240441259 |
240441259 |
0 |
0 |
T1 |
107483 |
107483 |
0 |
0 |
T2 |
101749 |
101749 |
0 |
0 |
T4 |
13103 |
13103 |
0 |
0 |
T5 |
1858 |
1858 |
0 |
0 |
T6 |
889 |
889 |
0 |
0 |
T7 |
623 |
623 |
0 |
0 |
T16 |
1441 |
1441 |
0 |
0 |
T17 |
6671 |
6671 |
0 |
0 |
T18 |
1530 |
1530 |
0 |
0 |
T19 |
21178 |
21178 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
120220038 |
120220038 |
0 |
0 |
T1 |
53742 |
53742 |
0 |
0 |
T2 |
50875 |
50875 |
0 |
0 |
T4 |
6551 |
6551 |
0 |
0 |
T5 |
929 |
929 |
0 |
0 |
T6 |
444 |
444 |
0 |
0 |
T7 |
311 |
311 |
0 |
0 |
T16 |
721 |
721 |
0 |
0 |
T17 |
3335 |
3335 |
0 |
0 |
T18 |
765 |
765 |
0 |
0 |
T19 |
10589 |
10589 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
120220038 |
120220038 |
0 |
0 |
T1 |
53742 |
53742 |
0 |
0 |
T2 |
50875 |
50875 |
0 |
0 |
T4 |
6551 |
6551 |
0 |
0 |
T5 |
929 |
929 |
0 |
0 |
T6 |
444 |
444 |
0 |
0 |
T7 |
311 |
311 |
0 |
0 |
T16 |
721 |
721 |
0 |
0 |
T17 |
3335 |
3335 |
0 |
0 |
T18 |
765 |
765 |
0 |
0 |
T19 |
10589 |
10589 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
246945586 |
245866695 |
0 |
0 |
T1 |
107555 |
107488 |
0 |
0 |
T2 |
101793 |
101753 |
0 |
0 |
T4 |
20825 |
13099 |
0 |
0 |
T5 |
1859 |
1833 |
0 |
0 |
T6 |
862 |
809 |
0 |
0 |
T7 |
697 |
630 |
0 |
0 |
T16 |
1481 |
1441 |
0 |
0 |
T17 |
6725 |
6671 |
0 |
0 |
T18 |
1576 |
1530 |
0 |
0 |
T19 |
37049 |
21175 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
246945586 |
245866695 |
0 |
0 |
T1 |
107555 |
107488 |
0 |
0 |
T2 |
101793 |
101753 |
0 |
0 |
T4 |
20825 |
13099 |
0 |
0 |
T5 |
1859 |
1833 |
0 |
0 |
T6 |
862 |
809 |
0 |
0 |
T7 |
697 |
630 |
0 |
0 |
T16 |
1481 |
1441 |
0 |
0 |
T17 |
6725 |
6671 |
0 |
0 |
T18 |
1576 |
1530 |
0 |
0 |
T19 |
37049 |
21175 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168540206 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
929 |
903 |
0 |
3 |
T6 |
1779 |
1552 |
0 |
3 |
T7 |
1535 |
1291 |
0 |
3 |
T16 |
1358 |
1293 |
0 |
3 |
T17 |
3501 |
3449 |
0 |
3 |
T18 |
787 |
744 |
0 |
3 |
T19 |
38591 |
4961 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168540206 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
929 |
903 |
0 |
3 |
T6 |
1779 |
1552 |
0 |
3 |
T7 |
1535 |
1291 |
0 |
3 |
T16 |
1358 |
1293 |
0 |
3 |
T17 |
3501 |
3449 |
0 |
3 |
T18 |
787 |
744 |
0 |
3 |
T19 |
38591 |
4961 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168540206 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
929 |
903 |
0 |
3 |
T6 |
1779 |
1552 |
0 |
3 |
T7 |
1535 |
1291 |
0 |
3 |
T16 |
1358 |
1293 |
0 |
3 |
T17 |
3501 |
3449 |
0 |
3 |
T18 |
787 |
744 |
0 |
3 |
T19 |
38591 |
4961 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168540206 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
929 |
903 |
0 |
3 |
T6 |
1779 |
1552 |
0 |
3 |
T7 |
1535 |
1291 |
0 |
3 |
T16 |
1358 |
1293 |
0 |
3 |
T17 |
3501 |
3449 |
0 |
3 |
T18 |
787 |
744 |
0 |
3 |
T19 |
38591 |
4961 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168540206 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
929 |
903 |
0 |
3 |
T6 |
1779 |
1552 |
0 |
3 |
T7 |
1535 |
1291 |
0 |
3 |
T16 |
1358 |
1293 |
0 |
3 |
T17 |
3501 |
3449 |
0 |
3 |
T18 |
787 |
744 |
0 |
3 |
T19 |
38591 |
4961 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168540206 |
0 |
2415 |
T1 |
215101 |
214867 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
41649 |
2565 |
0 |
3 |
T5 |
929 |
903 |
0 |
3 |
T6 |
1779 |
1552 |
0 |
3 |
T7 |
1535 |
1291 |
0 |
3 |
T16 |
1358 |
1293 |
0 |
3 |
T17 |
3501 |
3449 |
0 |
3 |
T18 |
787 |
744 |
0 |
3 |
T19 |
38591 |
4961 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
171165075 |
168547378 |
0 |
0 |
T1 |
215101 |
214870 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
41649 |
2586 |
0 |
0 |
T5 |
929 |
906 |
0 |
0 |
T6 |
1779 |
1555 |
0 |
0 |
T7 |
1535 |
1294 |
0 |
0 |
T16 |
1358 |
1296 |
0 |
0 |
T17 |
3501 |
3452 |
0 |
0 |
T18 |
787 |
747 |
0 |
0 |
T19 |
38591 |
5012 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510246538 |
0 |
2415 |
T1 |
224071 |
223827 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
43387 |
2668 |
0 |
3 |
T5 |
3874 |
3773 |
0 |
3 |
T6 |
1797 |
1568 |
0 |
3 |
T7 |
1422 |
1178 |
0 |
3 |
T16 |
3086 |
2942 |
0 |
3 |
T17 |
14009 |
13808 |
0 |
3 |
T18 |
3284 |
3112 |
0 |
3 |
T19 |
77184 |
9962 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
35179 |
0 |
0 |
T1 |
224071 |
1 |
0 |
0 |
T2 |
212066 |
1 |
0 |
0 |
T4 |
43387 |
7 |
0 |
0 |
T5 |
3874 |
7 |
0 |
0 |
T6 |
1797 |
7 |
0 |
0 |
T7 |
1422 |
9 |
0 |
0 |
T16 |
3086 |
3 |
0 |
0 |
T17 |
14009 |
67 |
0 |
0 |
T18 |
3284 |
3 |
0 |
0 |
T19 |
77184 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510246538 |
0 |
2415 |
T1 |
224071 |
223827 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
43387 |
2668 |
0 |
3 |
T5 |
3874 |
3773 |
0 |
3 |
T6 |
1797 |
1568 |
0 |
3 |
T7 |
1422 |
1178 |
0 |
3 |
T16 |
3086 |
2942 |
0 |
3 |
T17 |
14009 |
13808 |
0 |
3 |
T18 |
3284 |
3112 |
0 |
3 |
T19 |
77184 |
9962 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
34827 |
0 |
0 |
T1 |
224071 |
1 |
0 |
0 |
T2 |
212066 |
1 |
0 |
0 |
T4 |
43387 |
7 |
0 |
0 |
T5 |
3874 |
5 |
0 |
0 |
T6 |
1797 |
3 |
0 |
0 |
T7 |
1422 |
5 |
0 |
0 |
T16 |
3086 |
3 |
0 |
0 |
T17 |
14009 |
69 |
0 |
0 |
T18 |
3284 |
3 |
0 |
0 |
T19 |
77184 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510246538 |
0 |
2415 |
T1 |
224071 |
223827 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
43387 |
2668 |
0 |
3 |
T5 |
3874 |
3773 |
0 |
3 |
T6 |
1797 |
1568 |
0 |
3 |
T7 |
1422 |
1178 |
0 |
3 |
T16 |
3086 |
2942 |
0 |
3 |
T17 |
14009 |
13808 |
0 |
3 |
T18 |
3284 |
3112 |
0 |
3 |
T19 |
77184 |
9962 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
34985 |
0 |
0 |
T1 |
224071 |
1 |
0 |
0 |
T2 |
212066 |
1 |
0 |
0 |
T4 |
43387 |
7 |
0 |
0 |
T5 |
3874 |
5 |
0 |
0 |
T6 |
1797 |
7 |
0 |
0 |
T7 |
1422 |
15 |
0 |
0 |
T16 |
3086 |
3 |
0 |
0 |
T17 |
14009 |
62 |
0 |
0 |
T18 |
3284 |
3 |
0 |
0 |
T19 |
77184 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510246538 |
0 |
2415 |
T1 |
224071 |
223827 |
0 |
3 |
T2 |
212066 |
211866 |
0 |
3 |
T4 |
43387 |
2668 |
0 |
3 |
T5 |
3874 |
3773 |
0 |
3 |
T6 |
1797 |
1568 |
0 |
3 |
T7 |
1422 |
1178 |
0 |
3 |
T16 |
3086 |
2942 |
0 |
3 |
T17 |
14009 |
13808 |
0 |
3 |
T18 |
3284 |
3112 |
0 |
3 |
T19 |
77184 |
9962 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
34685 |
0 |
0 |
T1 |
224071 |
1 |
0 |
0 |
T2 |
212066 |
1 |
0 |
0 |
T4 |
43387 |
7 |
0 |
0 |
T5 |
3874 |
5 |
0 |
0 |
T6 |
1797 |
3 |
0 |
0 |
T7 |
1422 |
12 |
0 |
0 |
T16 |
3086 |
3 |
0 |
0 |
T17 |
14009 |
72 |
0 |
0 |
T18 |
3284 |
3 |
0 |
0 |
T19 |
77184 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
514803257 |
510253624 |
0 |
0 |
T1 |
224071 |
223830 |
0 |
0 |
T2 |
212066 |
211869 |
0 |
0 |
T4 |
43387 |
2689 |
0 |
0 |
T5 |
3874 |
3776 |
0 |
0 |
T6 |
1797 |
1571 |
0 |
0 |
T7 |
1422 |
1181 |
0 |
0 |
T16 |
3086 |
2945 |
0 |
0 |
T17 |
14009 |
13811 |
0 |
0 |
T18 |
3284 |
3115 |
0 |
0 |
T19 |
77184 |
10001 |
0 |
0 |