Module Definition
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Module Instance : tb.dut.u_clk_main_aes_trans

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cg 100.00 100.00 100.00 100.00
u_en_sync 100.00 100.00 100.00
u_err_sync 100.00 100.00 100.00
u_hint_sync 100.00 100.00 100.00
u_idle_cnt 100.00 100.00
u_idle_sync 100.00 100.00 100.00 100.00 100.00
u_prim_buf_en 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cg 100.00 100.00 100.00 100.00
u_en_sync 100.00 100.00 100.00
u_err_sync 100.00 100.00 100.00
u_hint_sync 100.00 100.00 100.00
u_idle_cnt 100.00 100.00
u_idle_sync 100.00 100.00 100.00 100.00 100.00
u_prim_buf_en 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cg 100.00 100.00 100.00 100.00
u_en_sync 100.00 100.00 100.00
u_err_sync 100.00 100.00 100.00
u_hint_sync 100.00 100.00 100.00
u_idle_cnt 100.00 100.00
u_idle_sync 100.00 100.00 100.00 100.00 100.00
u_prim_buf_en 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cg 100.00 100.00 100.00 100.00
u_en_sync 100.00 100.00 100.00
u_err_sync 100.00 100.00 100.00
u_hint_sync 100.00 100.00 100.00
u_idle_cnt 100.00 100.00
u_idle_sync 100.00 100.00 100.00 100.00 100.00
u_prim_buf_en 100.00 100.00
u_prim_mubi4_sender 100.00 100.00 100.00 100.00
u_scanmode_sync 100.00 100.00 100.00

Line Coverage for Module : clkmgr_trans
Line No.TotalCoveredPercent
TOTAL99100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS14044100.00
ALWAYS15833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
140 1 1
141 1 1
142 1 1
143 1 1
MISSING_ELSE
158 1 1
159 1 1
161 1 1


Cond Coverage for Module : clkmgr_trans
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------
-1--2-StatusTests
00CoveredT17,T22,T3
01CoveredT5,T6,T7
10CoveredT5,T6,T7

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-
-1--2-StatusTests
01CoveredT17,T22,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

Branch Coverage for Module : clkmgr_trans
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 125 2 2 100.00
IF 140 3 3 100.00
IF 158 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 125 (combined_en_d) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 140 if ((!rst_ni)) -2-: 142 if (cnt_err)

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T7
0 1 Covered T33,T34,T45
0 0 Covered T5,T6,T7


LineNo. Expression -1-: 158 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans
Line No.TotalCoveredPercent
TOTAL99100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS14044100.00
ALWAYS15833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
140 1 1
141 1 1
142 1 1
143 1 1
MISSING_ELSE
158 1 1
159 1 1
161 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------
-1--2-StatusTests
00CoveredT17,T22,T3
01CoveredT5,T6,T7
10CoveredT5,T6,T7

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-
-1--2-StatusTests
01CoveredT17,T22,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 125 2 2 100.00
IF 140 3 3 100.00
IF 158 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 125 (combined_en_d) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 140 if ((!rst_ni)) -2-: 142 if (cnt_err)

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T7
0 1 Covered T33,T34,T45
0 0 Covered T5,T6,T7


LineNo. Expression -1-: 158 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans
Line No.TotalCoveredPercent
TOTAL99100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS14044100.00
ALWAYS15833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
140 1 1
141 1 1
142 1 1
143 1 1
MISSING_ELSE
158 1 1
159 1 1
161 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------
-1--2-StatusTests
00CoveredT17,T22,T3
01CoveredT5,T6,T7
10CoveredT5,T6,T7

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-
-1--2-StatusTests
01CoveredT17,T22,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 125 2 2 100.00
IF 140 3 3 100.00
IF 158 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 125 (combined_en_d) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 140 if ((!rst_ni)) -2-: 142 if (cnt_err)

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T7
0 1 Covered T33,T34,T45
0 0 Covered T5,T6,T7


LineNo. Expression -1-: 158 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans
Line No.TotalCoveredPercent
TOTAL99100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS14044100.00
ALWAYS15833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
140 1 1
141 1 1
142 1 1
143 1 1
MISSING_ELSE
158 1 1
159 1 1
161 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------
-1--2-StatusTests
00CoveredT17,T22,T3
01CoveredT5,T6,T7
10CoveredT5,T6,T7

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-
-1--2-StatusTests
01CoveredT17,T22,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 125 2 2 100.00
IF 140 3 3 100.00
IF 158 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 125 (combined_en_d) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 140 if ((!rst_ni)) -2-: 142 if (cnt_err)

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T7
0 1 Covered T33,T34,T45
0 0 Covered T5,T6,T7


LineNo. Expression -1-: 158 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans
Line No.TotalCoveredPercent
TOTAL99100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4611100.00
ALWAYS14044100.00
ALWAYS15833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
46 1 1
140 1 1
141 1 1
142 1 1
143 1 1
MISSING_ELSE
158 1 1
159 1 1
161 1 1


Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------
-1--2-StatusTests
00CoveredT17,T22,T3
01CoveredT5,T6,T7
10CoveredT5,T6,T7

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-
-1--2-StatusTests
01CoveredT17,T22,T3
10CoveredT5,T6,T7
11CoveredT5,T6,T7

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT5,T6,T7

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 125 2 2 100.00
IF 140 3 3 100.00
IF 158 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 125 (combined_en_d) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 140 if ((!rst_ni)) -2-: 142 if (cnt_err)

Branches:
-1--2-StatusTests
1 - Covered T5,T6,T7
0 1 Covered T33,T34,T45
0 0 Covered T5,T6,T7


LineNo. Expression -1-: 158 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%