Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
961903 |
0 |
0 |
T1 |
3083618 |
2685 |
0 |
0 |
T2 |
2061326 |
1250 |
0 |
0 |
T3 |
0 |
130 |
0 |
0 |
T9 |
0 |
822 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T11 |
0 |
1384 |
0 |
0 |
T12 |
0 |
10695 |
0 |
0 |
T13 |
0 |
2573 |
0 |
0 |
T16 |
22594 |
0 |
0 |
0 |
T17 |
33660 |
0 |
0 |
0 |
T18 |
14982 |
0 |
0 |
0 |
T19 |
18888 |
0 |
0 |
0 |
T20 |
7108 |
0 |
0 |
0 |
T21 |
7285 |
0 |
0 |
0 |
T22 |
13061 |
0 |
0 |
0 |
T23 |
69527 |
0 |
0 |
0 |
T24 |
0 |
100 |
0 |
0 |
T27 |
0 |
110 |
0 |
0 |
T28 |
0 |
972 |
0 |
0 |
T29 |
0 |
532 |
0 |
0 |
T49 |
8238 |
1 |
0 |
0 |
T50 |
18242 |
1 |
0 |
0 |
T53 |
7204 |
2 |
0 |
0 |
T54 |
5686 |
1 |
0 |
0 |
T57 |
30298 |
1 |
0 |
0 |
T109 |
18936 |
2 |
0 |
0 |
T110 |
17966 |
3 |
0 |
0 |
T111 |
10959 |
1 |
0 |
0 |
T112 |
12810 |
1 |
0 |
0 |
T113 |
5182 |
0 |
0 |
0 |
T114 |
14024 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
959445 |
0 |
0 |
T1 |
2792117 |
2685 |
0 |
0 |
T2 |
439426 |
1250 |
0 |
0 |
T3 |
0 |
130 |
0 |
0 |
T9 |
0 |
822 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T11 |
0 |
1384 |
0 |
0 |
T12 |
0 |
10599 |
0 |
0 |
T13 |
0 |
2573 |
0 |
0 |
T16 |
7285 |
0 |
0 |
0 |
T17 |
10762 |
0 |
0 |
0 |
T18 |
8953 |
0 |
0 |
0 |
T19 |
6211 |
0 |
0 |
0 |
T20 |
4306 |
0 |
0 |
0 |
T21 |
4509 |
0 |
0 |
0 |
T22 |
7526 |
0 |
0 |
0 |
T23 |
18588 |
0 |
0 |
0 |
T24 |
0 |
100 |
0 |
0 |
T27 |
0 |
110 |
0 |
0 |
T28 |
0 |
972 |
0 |
0 |
T29 |
0 |
532 |
0 |
0 |
T49 |
7090 |
1 |
0 |
0 |
T50 |
33076 |
1 |
0 |
0 |
T53 |
14088 |
2 |
0 |
0 |
T54 |
44594 |
1 |
0 |
0 |
T57 |
13296 |
1 |
0 |
0 |
T109 |
35908 |
2 |
0 |
0 |
T110 |
7506 |
3 |
0 |
0 |
T111 |
27018 |
1 |
0 |
0 |
T112 |
34302 |
1 |
0 |
0 |
T113 |
9082 |
0 |
0 |
0 |
T114 |
8190 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441544108 |
25583 |
0 |
0 |
T1 |
764386 |
126 |
0 |
0 |
T2 |
508696 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
5386 |
0 |
0 |
0 |
T17 |
8381 |
0 |
0 |
0 |
T18 |
3129 |
0 |
0 |
0 |
T19 |
4737 |
0 |
0 |
0 |
T20 |
1467 |
0 |
0 |
0 |
T21 |
1547 |
0 |
0 |
0 |
T22 |
2604 |
0 |
0 |
0 |
T23 |
16524 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441544108 |
31434 |
0 |
0 |
T1 |
764386 |
130 |
0 |
0 |
T2 |
508696 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
5386 |
0 |
0 |
0 |
T17 |
8381 |
0 |
0 |
0 |
T18 |
3129 |
0 |
0 |
0 |
T19 |
4737 |
0 |
0 |
0 |
T20 |
1467 |
0 |
0 |
0 |
T21 |
1547 |
0 |
0 |
0 |
T22 |
2604 |
0 |
0 |
0 |
T23 |
16524 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31447 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31423 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441544108 |
31436 |
0 |
0 |
T1 |
764386 |
130 |
0 |
0 |
T2 |
508696 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
5386 |
0 |
0 |
0 |
T17 |
8381 |
0 |
0 |
0 |
T18 |
3129 |
0 |
0 |
0 |
T19 |
4737 |
0 |
0 |
0 |
T20 |
1467 |
0 |
0 |
0 |
T21 |
1547 |
0 |
0 |
0 |
T22 |
2604 |
0 |
0 |
0 |
T23 |
16524 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219828736 |
25583 |
0 |
0 |
T1 |
382407 |
126 |
0 |
0 |
T2 |
257866 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
2913 |
0 |
0 |
0 |
T17 |
4130 |
0 |
0 |
0 |
T18 |
1525 |
0 |
0 |
0 |
T19 |
2301 |
0 |
0 |
0 |
T20 |
714 |
0 |
0 |
0 |
T21 |
713 |
0 |
0 |
0 |
T22 |
1454 |
0 |
0 |
0 |
T23 |
9636 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219828736 |
31554 |
0 |
0 |
T1 |
382407 |
130 |
0 |
0 |
T2 |
257866 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
2913 |
0 |
0 |
0 |
T17 |
4130 |
0 |
0 |
0 |
T18 |
1525 |
0 |
0 |
0 |
T19 |
2301 |
0 |
0 |
0 |
T20 |
714 |
0 |
0 |
0 |
T21 |
713 |
0 |
0 |
0 |
T22 |
1454 |
0 |
0 |
0 |
T23 |
9636 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31582 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31548 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219828736 |
31556 |
0 |
0 |
T1 |
382407 |
130 |
0 |
0 |
T2 |
257866 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
2913 |
0 |
0 |
0 |
T17 |
4130 |
0 |
0 |
0 |
T18 |
1525 |
0 |
0 |
0 |
T19 |
2301 |
0 |
0 |
0 |
T20 |
714 |
0 |
0 |
0 |
T21 |
713 |
0 |
0 |
0 |
T22 |
1454 |
0 |
0 |
0 |
T23 |
9636 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109913787 |
25583 |
0 |
0 |
T1 |
191203 |
126 |
0 |
0 |
T2 |
128932 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1456 |
0 |
0 |
0 |
T17 |
2065 |
0 |
0 |
0 |
T18 |
762 |
0 |
0 |
0 |
T19 |
1151 |
0 |
0 |
0 |
T20 |
357 |
0 |
0 |
0 |
T21 |
357 |
0 |
0 |
0 |
T22 |
725 |
0 |
0 |
0 |
T23 |
4817 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109913787 |
31354 |
0 |
0 |
T1 |
191203 |
130 |
0 |
0 |
T2 |
128932 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1456 |
0 |
0 |
0 |
T17 |
2065 |
0 |
0 |
0 |
T18 |
762 |
0 |
0 |
0 |
T19 |
1151 |
0 |
0 |
0 |
T20 |
357 |
0 |
0 |
0 |
T21 |
357 |
0 |
0 |
0 |
T22 |
725 |
0 |
0 |
0 |
T23 |
4817 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31382 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31350 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109913787 |
31361 |
0 |
0 |
T1 |
191203 |
130 |
0 |
0 |
T2 |
128932 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1456 |
0 |
0 |
0 |
T17 |
2065 |
0 |
0 |
0 |
T18 |
762 |
0 |
0 |
0 |
T19 |
1151 |
0 |
0 |
0 |
T20 |
357 |
0 |
0 |
0 |
T21 |
357 |
0 |
0 |
0 |
T22 |
725 |
0 |
0 |
0 |
T23 |
4817 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471054484 |
25583 |
0 |
0 |
T1 |
802861 |
126 |
0 |
0 |
T2 |
589910 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
5611 |
0 |
0 |
0 |
T17 |
8730 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
4882 |
0 |
0 |
0 |
T20 |
1576 |
0 |
0 |
0 |
T21 |
1582 |
0 |
0 |
0 |
T22 |
2712 |
0 |
0 |
0 |
T23 |
17212 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471054484 |
31312 |
0 |
0 |
T1 |
802861 |
130 |
0 |
0 |
T2 |
589910 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
5611 |
0 |
0 |
0 |
T17 |
8730 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
4882 |
0 |
0 |
0 |
T20 |
1576 |
0 |
0 |
0 |
T21 |
1582 |
0 |
0 |
0 |
T22 |
2712 |
0 |
0 |
0 |
T23 |
17212 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31323 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31303 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471054484 |
31314 |
0 |
0 |
T1 |
802861 |
130 |
0 |
0 |
T2 |
589910 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
5611 |
0 |
0 |
0 |
T17 |
8730 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
4882 |
0 |
0 |
0 |
T20 |
1576 |
0 |
0 |
0 |
T21 |
1582 |
0 |
0 |
0 |
T22 |
2712 |
0 |
0 |
0 |
T23 |
17212 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226192637 |
25172 |
0 |
0 |
T1 |
386531 |
126 |
0 |
0 |
T2 |
280281 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
2693 |
0 |
0 |
0 |
T17 |
4190 |
0 |
0 |
0 |
T18 |
1564 |
0 |
0 |
0 |
T19 |
2357 |
0 |
0 |
0 |
T20 |
759 |
0 |
0 |
0 |
T21 |
798 |
0 |
0 |
0 |
T22 |
1301 |
0 |
0 |
0 |
T23 |
8262 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T27 |
0 |
11 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226192637 |
31283 |
0 |
0 |
T1 |
386531 |
130 |
0 |
0 |
T2 |
280281 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
2693 |
0 |
0 |
0 |
T17 |
4190 |
0 |
0 |
0 |
T18 |
1564 |
0 |
0 |
0 |
T19 |
2357 |
0 |
0 |
0 |
T20 |
759 |
0 |
0 |
0 |
T21 |
798 |
0 |
0 |
0 |
T22 |
1301 |
0 |
0 |
0 |
T23 |
8262 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31433 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31082 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
38 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226192637 |
31314 |
0 |
0 |
T1 |
386531 |
130 |
0 |
0 |
T2 |
280281 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
2693 |
0 |
0 |
0 |
T17 |
4190 |
0 |
0 |
0 |
T18 |
1564 |
0 |
0 |
0 |
T19 |
2357 |
0 |
0 |
0 |
T20 |
759 |
0 |
0 |
0 |
T21 |
798 |
0 |
0 |
0 |
T22 |
1301 |
0 |
0 |
0 |
T23 |
8262 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T48,T49,T50 |
1 | 0 | Covered | T48,T49,T50 |
1 | 1 | Covered | T109,T115,T116 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T48,T49,T50 |
1 | 0 | Covered | T109,T115,T116 |
1 | 1 | Covered | T48,T49,T50 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
39 |
0 |
0 |
T48 |
8740 |
1 |
0 |
0 |
T49 |
4119 |
1 |
0 |
0 |
T50 |
9121 |
2 |
0 |
0 |
T51 |
4120 |
1 |
0 |
0 |
T55 |
3148 |
1 |
0 |
0 |
T58 |
12151 |
1 |
0 |
0 |
T109 |
9468 |
3 |
0 |
0 |
T110 |
8983 |
1 |
0 |
0 |
T111 |
10959 |
1 |
0 |
0 |
T112 |
6405 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441544108 |
39 |
0 |
0 |
T48 |
8560 |
1 |
0 |
0 |
T49 |
8071 |
1 |
0 |
0 |
T50 |
35025 |
2 |
0 |
0 |
T51 |
14650 |
1 |
0 |
0 |
T55 |
12594 |
1 |
0 |
0 |
T58 |
68617 |
1 |
0 |
0 |
T109 |
37872 |
3 |
0 |
0 |
T110 |
8983 |
1 |
0 |
0 |
T111 |
55373 |
1 |
0 |
0 |
T112 |
36170 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T50,T51 |
1 | 0 | Covered | T49,T50,T51 |
1 | 1 | Covered | T109,T112,T115 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T50,T51 |
1 | 0 | Covered | T109,T112,T115 |
1 | 1 | Covered | T49,T50,T51 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
33 |
0 |
0 |
T49 |
4119 |
1 |
0 |
0 |
T50 |
9121 |
1 |
0 |
0 |
T51 |
4120 |
1 |
0 |
0 |
T52 |
3493 |
1 |
0 |
0 |
T55 |
3148 |
1 |
0 |
0 |
T109 |
9468 |
2 |
0 |
0 |
T110 |
8983 |
1 |
0 |
0 |
T112 |
6405 |
2 |
0 |
0 |
T114 |
14024 |
2 |
0 |
0 |
T117 |
3107 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441544108 |
33 |
0 |
0 |
T49 |
8071 |
1 |
0 |
0 |
T50 |
35025 |
1 |
0 |
0 |
T51 |
14650 |
1 |
0 |
0 |
T52 |
12899 |
1 |
0 |
0 |
T55 |
12594 |
1 |
0 |
0 |
T109 |
37872 |
2 |
0 |
0 |
T110 |
8983 |
1 |
0 |
0 |
T112 |
36170 |
2 |
0 |
0 |
T114 |
18699 |
2 |
0 |
0 |
T117 |
42617 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T50,T53 |
1 | 0 | Covered | T49,T50,T53 |
1 | 1 | Covered | T110,T113,T115 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T50,T53 |
1 | 0 | Covered | T110,T113,T115 |
1 | 1 | Covered | T49,T50,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
34 |
0 |
0 |
T49 |
4119 |
1 |
0 |
0 |
T50 |
9121 |
1 |
0 |
0 |
T53 |
3602 |
2 |
0 |
0 |
T54 |
2843 |
1 |
0 |
0 |
T57 |
15149 |
1 |
0 |
0 |
T109 |
9468 |
2 |
0 |
0 |
T110 |
8983 |
3 |
0 |
0 |
T111 |
10959 |
1 |
0 |
0 |
T112 |
6405 |
1 |
0 |
0 |
T113 |
2591 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219828736 |
34 |
0 |
0 |
T49 |
3545 |
1 |
0 |
0 |
T50 |
16538 |
1 |
0 |
0 |
T53 |
7044 |
2 |
0 |
0 |
T54 |
22297 |
1 |
0 |
0 |
T57 |
6648 |
1 |
0 |
0 |
T109 |
17954 |
2 |
0 |
0 |
T110 |
3753 |
3 |
0 |
0 |
T111 |
27018 |
1 |
0 |
0 |
T112 |
17151 |
1 |
0 |
0 |
T113 |
4541 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T50,T53 |
1 | 0 | Covered | T49,T50,T53 |
1 | 1 | Covered | T50,T118,T115 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T50,T53 |
1 | 0 | Covered | T50,T118,T115 |
1 | 1 | Covered | T49,T50,T53 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
34 |
0 |
0 |
T49 |
4119 |
1 |
0 |
0 |
T50 |
9121 |
3 |
0 |
0 |
T53 |
3602 |
2 |
0 |
0 |
T54 |
2843 |
1 |
0 |
0 |
T57 |
15149 |
1 |
0 |
0 |
T109 |
9468 |
1 |
0 |
0 |
T110 |
8983 |
2 |
0 |
0 |
T112 |
6405 |
1 |
0 |
0 |
T113 |
2591 |
1 |
0 |
0 |
T114 |
14024 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219828736 |
34 |
0 |
0 |
T49 |
3545 |
1 |
0 |
0 |
T50 |
16538 |
3 |
0 |
0 |
T53 |
7044 |
2 |
0 |
0 |
T54 |
22297 |
1 |
0 |
0 |
T57 |
6648 |
1 |
0 |
0 |
T109 |
17954 |
1 |
0 |
0 |
T110 |
3753 |
2 |
0 |
0 |
T112 |
17151 |
1 |
0 |
0 |
T113 |
4541 |
1 |
0 |
0 |
T114 |
8190 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T56,T51 |
1 | 0 | Covered | T49,T56,T51 |
1 | 1 | Covered | T51,T110,T117 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T56,T51 |
1 | 0 | Covered | T51,T110,T117 |
1 | 1 | Covered | T49,T56,T51 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
22 |
0 |
0 |
T49 |
4119 |
1 |
0 |
0 |
T51 |
4120 |
2 |
0 |
0 |
T55 |
3148 |
1 |
0 |
0 |
T56 |
7630 |
1 |
0 |
0 |
T110 |
8983 |
3 |
0 |
0 |
T113 |
2591 |
1 |
0 |
0 |
T117 |
3107 |
4 |
0 |
0 |
T118 |
7533 |
1 |
0 |
0 |
T119 |
11932 |
1 |
0 |
0 |
T120 |
5259 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109913787 |
22 |
0 |
0 |
T49 |
1774 |
1 |
0 |
0 |
T51 |
3428 |
2 |
0 |
0 |
T55 |
2945 |
1 |
0 |
0 |
T56 |
1653 |
1 |
0 |
0 |
T110 |
1877 |
3 |
0 |
0 |
T113 |
2269 |
1 |
0 |
0 |
T117 |
10323 |
4 |
0 |
0 |
T118 |
3500 |
1 |
0 |
0 |
T119 |
2531 |
1 |
0 |
0 |
T120 |
2365 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T56,T51,T52 |
1 | 0 | Covered | T56,T51,T52 |
1 | 1 | Covered | T51,T112,T113 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T56,T51,T52 |
1 | 0 | Covered | T51,T112,T113 |
1 | 1 | Covered | T56,T51,T52 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
26 |
0 |
0 |
T51 |
4120 |
2 |
0 |
0 |
T52 |
3493 |
1 |
0 |
0 |
T54 |
2843 |
1 |
0 |
0 |
T56 |
7630 |
1 |
0 |
0 |
T110 |
8983 |
2 |
0 |
0 |
T111 |
10959 |
1 |
0 |
0 |
T112 |
6405 |
3 |
0 |
0 |
T113 |
2591 |
2 |
0 |
0 |
T117 |
3107 |
3 |
0 |
0 |
T121 |
7146 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109913787 |
26 |
0 |
0 |
T51 |
3428 |
2 |
0 |
0 |
T52 |
2977 |
1 |
0 |
0 |
T54 |
11147 |
1 |
0 |
0 |
T56 |
1653 |
1 |
0 |
0 |
T110 |
1877 |
2 |
0 |
0 |
T111 |
13511 |
1 |
0 |
0 |
T112 |
8576 |
3 |
0 |
0 |
T113 |
2269 |
2 |
0 |
0 |
T117 |
10323 |
3 |
0 |
0 |
T121 |
11954 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T50,T53,T58 |
1 | 0 | Covered | T50,T53,T58 |
1 | 1 | Covered | T112,T117,T114 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T50,T53,T58 |
1 | 0 | Covered | T112,T117,T114 |
1 | 1 | Covered | T50,T53,T58 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31 |
0 |
0 |
T50 |
9121 |
1 |
0 |
0 |
T53 |
3602 |
1 |
0 |
0 |
T55 |
3148 |
1 |
0 |
0 |
T57 |
15149 |
1 |
0 |
0 |
T58 |
12151 |
1 |
0 |
0 |
T111 |
10959 |
1 |
0 |
0 |
T112 |
6405 |
3 |
0 |
0 |
T121 |
7146 |
1 |
0 |
0 |
T122 |
11129 |
1 |
0 |
0 |
T123 |
4540 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471054484 |
31 |
0 |
0 |
T50 |
36486 |
1 |
0 |
0 |
T53 |
15663 |
1 |
0 |
0 |
T55 |
13120 |
1 |
0 |
0 |
T57 |
15149 |
1 |
0 |
0 |
T58 |
71479 |
1 |
0 |
0 |
T111 |
57683 |
1 |
0 |
0 |
T112 |
37678 |
3 |
0 |
0 |
T121 |
51044 |
1 |
0 |
0 |
T122 |
23187 |
1 |
0 |
0 |
T123 |
9266 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T53,T58,T55 |
1 | 0 | Covered | T53,T58,T55 |
1 | 1 | Covered | T58,T112,T117 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T53,T58,T55 |
1 | 0 | Covered | T58,T112,T117 |
1 | 1 | Covered | T53,T58,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
29 |
0 |
0 |
T53 |
3602 |
1 |
0 |
0 |
T55 |
3148 |
1 |
0 |
0 |
T57 |
15149 |
1 |
0 |
0 |
T58 |
12151 |
2 |
0 |
0 |
T111 |
10959 |
1 |
0 |
0 |
T112 |
6405 |
2 |
0 |
0 |
T113 |
2591 |
1 |
0 |
0 |
T121 |
7146 |
1 |
0 |
0 |
T122 |
11129 |
1 |
0 |
0 |
T123 |
4540 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471054484 |
29 |
0 |
0 |
T53 |
15663 |
1 |
0 |
0 |
T55 |
13120 |
1 |
0 |
0 |
T57 |
15149 |
1 |
0 |
0 |
T58 |
71479 |
2 |
0 |
0 |
T111 |
57683 |
1 |
0 |
0 |
T112 |
37678 |
2 |
0 |
0 |
T113 |
10366 |
1 |
0 |
0 |
T121 |
51044 |
1 |
0 |
0 |
T122 |
23187 |
1 |
0 |
0 |
T123 |
9266 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T50,T52,T55 |
1 | 0 | Covered | T50,T52,T55 |
1 | 1 | Covered | T122,T110,T112 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T50,T52,T55 |
1 | 0 | Covered | T122,T110,T112 |
1 | 1 | Covered | T50,T52,T55 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
33 |
0 |
0 |
T50 |
9121 |
2 |
0 |
0 |
T52 |
3493 |
1 |
0 |
0 |
T55 |
3148 |
1 |
0 |
0 |
T109 |
9468 |
1 |
0 |
0 |
T110 |
8983 |
2 |
0 |
0 |
T111 |
10959 |
1 |
0 |
0 |
T112 |
6405 |
2 |
0 |
0 |
T113 |
2591 |
1 |
0 |
0 |
T121 |
7146 |
1 |
0 |
0 |
T122 |
11129 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226192637 |
33 |
0 |
0 |
T50 |
17514 |
2 |
0 |
0 |
T52 |
6450 |
1 |
0 |
0 |
T55 |
6297 |
1 |
0 |
0 |
T109 |
18937 |
1 |
0 |
0 |
T110 |
4492 |
2 |
0 |
0 |
T111 |
27687 |
1 |
0 |
0 |
T112 |
18086 |
2 |
0 |
0 |
T113 |
4976 |
1 |
0 |
0 |
T121 |
24502 |
1 |
0 |
0 |
T122 |
11129 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T50,T52 |
1 | 0 | Covered | T49,T50,T52 |
1 | 1 | Covered | T122,T109,T110 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T49,T50,T52 |
1 | 0 | Covered | T122,T109,T110 |
1 | 1 | Covered | T49,T50,T52 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
35 |
0 |
0 |
T49 |
4119 |
1 |
0 |
0 |
T50 |
9121 |
4 |
0 |
0 |
T52 |
3493 |
1 |
0 |
0 |
T58 |
12151 |
1 |
0 |
0 |
T109 |
9468 |
2 |
0 |
0 |
T110 |
8983 |
2 |
0 |
0 |
T111 |
10959 |
1 |
0 |
0 |
T121 |
7146 |
1 |
0 |
0 |
T122 |
11129 |
3 |
0 |
0 |
T123 |
4540 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226192637 |
35 |
0 |
0 |
T49 |
4035 |
1 |
0 |
0 |
T50 |
17514 |
4 |
0 |
0 |
T52 |
6450 |
1 |
0 |
0 |
T58 |
34310 |
1 |
0 |
0 |
T109 |
18937 |
2 |
0 |
0 |
T110 |
4492 |
2 |
0 |
0 |
T111 |
27687 |
1 |
0 |
0 |
T121 |
24502 |
1 |
0 |
0 |
T122 |
11129 |
3 |
0 |
0 |
T123 |
4447 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
438700817 |
97271 |
0 |
0 |
T1 |
764386 |
542 |
0 |
0 |
T2 |
508696 |
263 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2108 |
0 |
0 |
T13 |
0 |
630 |
0 |
0 |
T16 |
5386 |
0 |
0 |
0 |
T17 |
8381 |
0 |
0 |
0 |
T18 |
3129 |
0 |
0 |
0 |
T19 |
4737 |
0 |
0 |
0 |
T20 |
1467 |
0 |
0 |
0 |
T21 |
1547 |
0 |
0 |
0 |
T22 |
2604 |
0 |
0 |
0 |
T23 |
16524 |
0 |
0 |
0 |
T28 |
0 |
201 |
0 |
0 |
T29 |
0 |
130 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16436946 |
96349 |
0 |
0 |
T1 |
513421 |
542 |
0 |
0 |
T2 |
15265 |
263 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2076 |
0 |
0 |
T13 |
0 |
630 |
0 |
0 |
T16 |
392 |
0 |
0 |
0 |
T17 |
611 |
0 |
0 |
0 |
T18 |
228 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
115 |
0 |
0 |
0 |
T21 |
119 |
0 |
0 |
0 |
T22 |
189 |
0 |
0 |
0 |
T23 |
1205 |
0 |
0 |
0 |
T28 |
0 |
201 |
0 |
0 |
T29 |
0 |
130 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218453085 |
96624 |
0 |
0 |
T1 |
382407 |
542 |
0 |
0 |
T2 |
257866 |
242 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2108 |
0 |
0 |
T13 |
0 |
628 |
0 |
0 |
T16 |
2913 |
0 |
0 |
0 |
T17 |
4130 |
0 |
0 |
0 |
T18 |
1525 |
0 |
0 |
0 |
T19 |
2301 |
0 |
0 |
0 |
T20 |
714 |
0 |
0 |
0 |
T21 |
713 |
0 |
0 |
0 |
T22 |
1454 |
0 |
0 |
0 |
T23 |
9636 |
0 |
0 |
0 |
T28 |
0 |
201 |
0 |
0 |
T29 |
0 |
130 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16436946 |
95715 |
0 |
0 |
T1 |
513421 |
542 |
0 |
0 |
T2 |
15265 |
242 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2076 |
0 |
0 |
T13 |
0 |
628 |
0 |
0 |
T16 |
392 |
0 |
0 |
0 |
T17 |
611 |
0 |
0 |
0 |
T18 |
228 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
115 |
0 |
0 |
0 |
T21 |
119 |
0 |
0 |
0 |
T22 |
189 |
0 |
0 |
0 |
T23 |
1205 |
0 |
0 |
0 |
T28 |
0 |
201 |
0 |
0 |
T29 |
0 |
130 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109225953 |
95465 |
0 |
0 |
T1 |
191203 |
542 |
0 |
0 |
T2 |
128932 |
236 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2105 |
0 |
0 |
T13 |
0 |
622 |
0 |
0 |
T16 |
1456 |
0 |
0 |
0 |
T17 |
2065 |
0 |
0 |
0 |
T18 |
762 |
0 |
0 |
0 |
T19 |
1151 |
0 |
0 |
0 |
T20 |
357 |
0 |
0 |
0 |
T21 |
357 |
0 |
0 |
0 |
T22 |
725 |
0 |
0 |
0 |
T23 |
4817 |
0 |
0 |
0 |
T28 |
0 |
201 |
0 |
0 |
T29 |
0 |
130 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
16436946 |
94582 |
0 |
0 |
T1 |
513421 |
542 |
0 |
0 |
T2 |
15265 |
236 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2073 |
0 |
0 |
T13 |
0 |
622 |
0 |
0 |
T16 |
392 |
0 |
0 |
0 |
T17 |
611 |
0 |
0 |
0 |
T18 |
228 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
115 |
0 |
0 |
0 |
T21 |
119 |
0 |
0 |
0 |
T22 |
189 |
0 |
0 |
0 |
T23 |
1205 |
0 |
0 |
0 |
T28 |
0 |
201 |
0 |
0 |
T29 |
0 |
130 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
468092615 |
116109 |
0 |
0 |
T1 |
802861 |
673 |
0 |
0 |
T2 |
589910 |
347 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2797 |
0 |
0 |
T13 |
0 |
693 |
0 |
0 |
T16 |
5611 |
0 |
0 |
0 |
T17 |
8730 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
4882 |
0 |
0 |
0 |
T20 |
1576 |
0 |
0 |
0 |
T21 |
1582 |
0 |
0 |
0 |
T22 |
2712 |
0 |
0 |
0 |
T23 |
17212 |
0 |
0 |
0 |
T28 |
0 |
249 |
0 |
0 |
T29 |
0 |
142 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17559044 |
115467 |
0 |
0 |
T1 |
513553 |
673 |
0 |
0 |
T2 |
15385 |
347 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2797 |
0 |
0 |
T13 |
0 |
693 |
0 |
0 |
T16 |
392 |
0 |
0 |
0 |
T17 |
611 |
0 |
0 |
0 |
T18 |
228 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
115 |
0 |
0 |
0 |
T21 |
119 |
0 |
0 |
0 |
T22 |
189 |
0 |
0 |
0 |
T23 |
1205 |
0 |
0 |
0 |
T28 |
0 |
249 |
0 |
0 |
T29 |
0 |
142 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
224770963 |
114971 |
0 |
0 |
T1 |
386531 |
721 |
0 |
0 |
T2 |
280281 |
325 |
0 |
0 |
T3 |
0 |
24 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2756 |
0 |
0 |
T13 |
0 |
688 |
0 |
0 |
T16 |
2693 |
0 |
0 |
0 |
T17 |
4190 |
0 |
0 |
0 |
T18 |
1564 |
0 |
0 |
0 |
T19 |
2357 |
0 |
0 |
0 |
T20 |
759 |
0 |
0 |
0 |
T21 |
798 |
0 |
0 |
0 |
T22 |
1301 |
0 |
0 |
0 |
T23 |
8262 |
0 |
0 |
0 |
T28 |
0 |
320 |
0 |
0 |
T29 |
0 |
154 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
17598194 |
114953 |
0 |
0 |
T1 |
513601 |
721 |
0 |
0 |
T2 |
15373 |
325 |
0 |
0 |
T3 |
0 |
24 |
0 |
0 |
T9 |
0 |
159 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
2756 |
0 |
0 |
T13 |
0 |
688 |
0 |
0 |
T16 |
392 |
0 |
0 |
0 |
T17 |
611 |
0 |
0 |
0 |
T18 |
228 |
0 |
0 |
0 |
T19 |
370 |
0 |
0 |
0 |
T20 |
115 |
0 |
0 |
0 |
T21 |
119 |
0 |
0 |
0 |
T22 |
189 |
0 |
0 |
0 |
T23 |
1205 |
0 |
0 |
0 |
T28 |
0 |
320 |
0 |
0 |
T29 |
0 |
154 |
0 |
0 |