Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 15 | 13 | 86.67 |
Logical | 15 | 13 | 86.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T24,T27 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1663522600 |
1483869 |
0 |
0 |
T1 |
1779470 |
4158 |
0 |
0 |
T2 |
601900 |
1461 |
0 |
0 |
T3 |
0 |
340 |
0 |
0 |
T9 |
0 |
5016 |
0 |
0 |
T10 |
0 |
1451 |
0 |
0 |
T11 |
0 |
5399 |
0 |
0 |
T12 |
0 |
18494 |
0 |
0 |
T16 |
14020 |
0 |
0 |
0 |
T17 |
20940 |
0 |
0 |
0 |
T18 |
32580 |
0 |
0 |
0 |
T19 |
12150 |
0 |
0 |
0 |
T20 |
15660 |
0 |
0 |
0 |
T21 |
16600 |
0 |
0 |
0 |
T22 |
26580 |
0 |
0 |
0 |
T23 |
20660 |
0 |
0 |
0 |
T24 |
0 |
2484 |
0 |
0 |
T27 |
0 |
2479 |
0 |
0 |
T28 |
0 |
1335 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5054776 |
5054236 |
0 |
0 |
T2 |
3531370 |
3525748 |
0 |
0 |
T4 |
18744 |
17368 |
0 |
0 |
T5 |
13578 |
12476 |
0 |
0 |
T6 |
54560 |
53530 |
0 |
0 |
T16 |
36118 |
34890 |
0 |
0 |
T17 |
54992 |
53746 |
0 |
0 |
T18 |
20476 |
19166 |
0 |
0 |
T19 |
30856 |
29446 |
0 |
0 |
T20 |
9746 |
9278 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1663522600 |
284170 |
0 |
0 |
T1 |
1779470 |
1280 |
0 |
0 |
T2 |
601900 |
540 |
0 |
0 |
T3 |
0 |
100 |
0 |
0 |
T9 |
0 |
620 |
0 |
0 |
T10 |
0 |
200 |
0 |
0 |
T11 |
0 |
1080 |
0 |
0 |
T12 |
0 |
5240 |
0 |
0 |
T16 |
14020 |
0 |
0 |
0 |
T17 |
20940 |
0 |
0 |
0 |
T18 |
32580 |
0 |
0 |
0 |
T19 |
12150 |
0 |
0 |
0 |
T20 |
15660 |
0 |
0 |
0 |
T21 |
16600 |
0 |
0 |
0 |
T22 |
26580 |
0 |
0 |
0 |
T23 |
20660 |
0 |
0 |
0 |
T24 |
0 |
292 |
0 |
0 |
T27 |
0 |
308 |
0 |
0 |
T28 |
0 |
400 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1663522600 |
1636877840 |
0 |
0 |
T1 |
1779470 |
1779260 |
0 |
0 |
T2 |
601900 |
600940 |
0 |
0 |
T4 |
28680 |
26380 |
0 |
0 |
T5 |
20230 |
18470 |
0 |
0 |
T6 |
15840 |
15520 |
0 |
0 |
T16 |
14020 |
13460 |
0 |
0 |
T17 |
20940 |
20410 |
0 |
0 |
T18 |
32580 |
30320 |
0 |
0 |
T19 |
12150 |
11570 |
0 |
0 |
T20 |
15660 |
14870 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
93545 |
0 |
0 |
T1 |
177947 |
308 |
0 |
0 |
T2 |
60190 |
137 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
312 |
0 |
0 |
T10 |
0 |
92 |
0 |
0 |
T11 |
0 |
378 |
0 |
0 |
T12 |
0 |
1365 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
124 |
0 |
0 |
T27 |
0 |
109 |
0 |
0 |
T28 |
0 |
100 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441544108 |
436881561 |
0 |
0 |
T1 |
764386 |
764293 |
0 |
0 |
T2 |
508696 |
507753 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
8006 |
7844 |
0 |
0 |
T16 |
5386 |
5169 |
0 |
0 |
T17 |
8381 |
8164 |
0 |
0 |
T18 |
3129 |
2912 |
0 |
0 |
T19 |
4737 |
4492 |
0 |
0 |
T20 |
1467 |
1387 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
135038 |
0 |
0 |
T1 |
177947 |
424 |
0 |
0 |
T2 |
60190 |
137 |
0 |
0 |
T3 |
0 |
35 |
0 |
0 |
T9 |
0 |
499 |
0 |
0 |
T10 |
0 |
142 |
0 |
0 |
T11 |
0 |
540 |
0 |
0 |
T12 |
0 |
1891 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
170 |
0 |
0 |
T27 |
0 |
173 |
0 |
0 |
T28 |
0 |
136 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219828736 |
218693966 |
0 |
0 |
T1 |
382407 |
382384 |
0 |
0 |
T2 |
257866 |
257590 |
0 |
0 |
T4 |
1388 |
1319 |
0 |
0 |
T5 |
1098 |
1029 |
0 |
0 |
T6 |
4621 |
4552 |
0 |
0 |
T16 |
2913 |
2872 |
0 |
0 |
T17 |
4130 |
4082 |
0 |
0 |
T18 |
1525 |
1456 |
0 |
0 |
T19 |
2301 |
2246 |
0 |
0 |
T20 |
714 |
693 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
216516 |
0 |
0 |
T1 |
177947 |
581 |
0 |
0 |
T2 |
60190 |
177 |
0 |
0 |
T3 |
0 |
50 |
0 |
0 |
T9 |
0 |
878 |
0 |
0 |
T10 |
0 |
252 |
0 |
0 |
T11 |
0 |
866 |
0 |
0 |
T12 |
0 |
2711 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
297 |
0 |
0 |
T27 |
0 |
308 |
0 |
0 |
T28 |
0 |
198 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109913787 |
109346525 |
0 |
0 |
T1 |
191203 |
191192 |
0 |
0 |
T2 |
128932 |
128794 |
0 |
0 |
T4 |
694 |
660 |
0 |
0 |
T5 |
548 |
513 |
0 |
0 |
T6 |
2310 |
2276 |
0 |
0 |
T16 |
1456 |
1435 |
0 |
0 |
T17 |
2065 |
2041 |
0 |
0 |
T18 |
762 |
728 |
0 |
0 |
T19 |
1151 |
1123 |
0 |
0 |
T20 |
357 |
347 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
91220 |
0 |
0 |
T1 |
177947 |
308 |
0 |
0 |
T2 |
60190 |
137 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
306 |
0 |
0 |
T10 |
0 |
90 |
0 |
0 |
T11 |
0 |
371 |
0 |
0 |
T12 |
0 |
1322 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
103 |
0 |
0 |
T27 |
0 |
107 |
0 |
0 |
T28 |
0 |
96 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471054484 |
466142080 |
0 |
0 |
T1 |
802861 |
802764 |
0 |
0 |
T2 |
589910 |
588929 |
0 |
0 |
T4 |
2988 |
2748 |
0 |
0 |
T5 |
2108 |
1925 |
0 |
0 |
T6 |
8340 |
8171 |
0 |
0 |
T16 |
5611 |
5385 |
0 |
0 |
T17 |
8730 |
8504 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
4882 |
4627 |
0 |
0 |
T20 |
1576 |
1492 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25583 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
131998 |
0 |
0 |
T1 |
177947 |
423 |
0 |
0 |
T2 |
60190 |
137 |
0 |
0 |
T3 |
0 |
35 |
0 |
0 |
T9 |
0 |
498 |
0 |
0 |
T10 |
0 |
145 |
0 |
0 |
T11 |
0 |
542 |
0 |
0 |
T12 |
0 |
1883 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
126 |
0 |
0 |
T27 |
0 |
98 |
0 |
0 |
T28 |
0 |
138 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226192637 |
223832873 |
0 |
0 |
T1 |
386531 |
386485 |
0 |
0 |
T2 |
280281 |
279808 |
0 |
0 |
T4 |
1434 |
1319 |
0 |
0 |
T5 |
1012 |
924 |
0 |
0 |
T6 |
4003 |
3922 |
0 |
0 |
T16 |
2693 |
2584 |
0 |
0 |
T17 |
4190 |
4082 |
0 |
0 |
T18 |
1564 |
1455 |
0 |
0 |
T19 |
2357 |
2235 |
0 |
0 |
T20 |
759 |
720 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
25072 |
0 |
0 |
T1 |
177947 |
126 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
519 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
12 |
0 |
0 |
T27 |
0 |
11 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T24,T27 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
113906 |
0 |
0 |
T1 |
177947 |
320 |
0 |
0 |
T2 |
60190 |
138 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
313 |
0 |
0 |
T10 |
0 |
93 |
0 |
0 |
T11 |
0 |
376 |
0 |
0 |
T12 |
0 |
1405 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
236 |
0 |
0 |
T27 |
0 |
223 |
0 |
0 |
T28 |
0 |
98 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
441544108 |
436881561 |
0 |
0 |
T1 |
764386 |
764293 |
0 |
0 |
T2 |
508696 |
507753 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
8006 |
7844 |
0 |
0 |
T16 |
5386 |
5169 |
0 |
0 |
T17 |
8381 |
8164 |
0 |
0 |
T18 |
3129 |
2912 |
0 |
0 |
T19 |
4737 |
4492 |
0 |
0 |
T20 |
1467 |
1387 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31425 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T24,T27 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
165069 |
0 |
0 |
T1 |
177947 |
434 |
0 |
0 |
T2 |
60190 |
138 |
0 |
0 |
T3 |
0 |
35 |
0 |
0 |
T9 |
0 |
506 |
0 |
0 |
T10 |
0 |
146 |
0 |
0 |
T11 |
0 |
543 |
0 |
0 |
T12 |
0 |
1913 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
333 |
0 |
0 |
T27 |
0 |
351 |
0 |
0 |
T28 |
0 |
137 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
219828736 |
218693966 |
0 |
0 |
T1 |
382407 |
382384 |
0 |
0 |
T2 |
257866 |
257590 |
0 |
0 |
T4 |
1388 |
1319 |
0 |
0 |
T5 |
1098 |
1029 |
0 |
0 |
T6 |
4621 |
4552 |
0 |
0 |
T16 |
2913 |
2872 |
0 |
0 |
T17 |
4130 |
4082 |
0 |
0 |
T18 |
1525 |
1456 |
0 |
0 |
T19 |
2301 |
2246 |
0 |
0 |
T20 |
714 |
693 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31549 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T24,T27 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
263237 |
0 |
0 |
T1 |
177947 |
605 |
0 |
0 |
T2 |
60190 |
184 |
0 |
0 |
T3 |
0 |
50 |
0 |
0 |
T9 |
0 |
886 |
0 |
0 |
T10 |
0 |
256 |
0 |
0 |
T11 |
0 |
874 |
0 |
0 |
T12 |
0 |
2742 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
583 |
0 |
0 |
T27 |
0 |
601 |
0 |
0 |
T28 |
0 |
197 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109913787 |
109346525 |
0 |
0 |
T1 |
191203 |
191192 |
0 |
0 |
T2 |
128932 |
128794 |
0 |
0 |
T4 |
694 |
660 |
0 |
0 |
T5 |
548 |
513 |
0 |
0 |
T6 |
2310 |
2276 |
0 |
0 |
T16 |
1456 |
1435 |
0 |
0 |
T17 |
2065 |
2041 |
0 |
0 |
T18 |
762 |
728 |
0 |
0 |
T19 |
1151 |
1123 |
0 |
0 |
T20 |
357 |
347 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31351 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T24,T27 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
110803 |
0 |
0 |
T1 |
177947 |
320 |
0 |
0 |
T2 |
60190 |
138 |
0 |
0 |
T3 |
0 |
25 |
0 |
0 |
T9 |
0 |
308 |
0 |
0 |
T10 |
0 |
89 |
0 |
0 |
T11 |
0 |
370 |
0 |
0 |
T12 |
0 |
1342 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
192 |
0 |
0 |
T27 |
0 |
214 |
0 |
0 |
T28 |
0 |
96 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
471054484 |
466142080 |
0 |
0 |
T1 |
802861 |
802764 |
0 |
0 |
T2 |
589910 |
588929 |
0 |
0 |
T4 |
2988 |
2748 |
0 |
0 |
T5 |
2108 |
1925 |
0 |
0 |
T6 |
8340 |
8171 |
0 |
0 |
T16 |
5611 |
5385 |
0 |
0 |
T17 |
8730 |
8504 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
4882 |
4627 |
0 |
0 |
T20 |
1576 |
1492 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31303 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T24,T27 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
162537 |
0 |
0 |
T1 |
177947 |
435 |
0 |
0 |
T2 |
60190 |
138 |
0 |
0 |
T3 |
0 |
35 |
0 |
0 |
T9 |
0 |
510 |
0 |
0 |
T10 |
0 |
146 |
0 |
0 |
T11 |
0 |
539 |
0 |
0 |
T12 |
0 |
1920 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
320 |
0 |
0 |
T27 |
0 |
295 |
0 |
0 |
T28 |
0 |
139 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
226192637 |
223832873 |
0 |
0 |
T1 |
386531 |
386485 |
0 |
0 |
T2 |
280281 |
279808 |
0 |
0 |
T4 |
1434 |
1319 |
0 |
0 |
T5 |
1012 |
924 |
0 |
0 |
T6 |
4003 |
3922 |
0 |
0 |
T16 |
2693 |
2584 |
0 |
0 |
T17 |
4190 |
4082 |
0 |
0 |
T18 |
1564 |
1455 |
0 |
0 |
T19 |
2357 |
2235 |
0 |
0 |
T20 |
759 |
720 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
31138 |
0 |
0 |
T1 |
177947 |
130 |
0 |
0 |
T2 |
60190 |
54 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
62 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
0 |
108 |
0 |
0 |
T12 |
0 |
529 |
0 |
0 |
T16 |
1402 |
0 |
0 |
0 |
T17 |
2094 |
0 |
0 |
0 |
T18 |
3258 |
0 |
0 |
0 |
T19 |
1215 |
0 |
0 |
0 |
T20 |
1566 |
0 |
0 |
0 |
T21 |
1660 |
0 |
0 |
0 |
T22 |
2658 |
0 |
0 |
0 |
T23 |
2066 |
0 |
0 |
0 |
T24 |
0 |
40 |
0 |
0 |
T27 |
0 |
33 |
0 |
0 |
T28 |
0 |
40 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166352260 |
163687784 |
0 |
0 |
T1 |
177947 |
177926 |
0 |
0 |
T2 |
60190 |
60094 |
0 |
0 |
T4 |
2868 |
2638 |
0 |
0 |
T5 |
2023 |
1847 |
0 |
0 |
T6 |
1584 |
1552 |
0 |
0 |
T16 |
1402 |
1346 |
0 |
0 |
T17 |
2094 |
2041 |
0 |
0 |
T18 |
3258 |
3032 |
0 |
0 |
T19 |
1215 |
1157 |
0 |
0 |
T20 |
1566 |
1487 |
0 |
0 |